On Fri, Jul 02, 2021 at 11:21:10AM +0200, Daniel Vetter wrote:
On Thu, Jul 1, 2021 at 10:26 PM Matt Roper matthew.d.roper@intel.com wrote:
From: Paulo Zanoni paulo.r.zanoni@intel.com
The current interrupt handler is getting increasingly complicated and Xe_HP changes will bring even more complexity. Let's split off a new interrupt handler starting with DG1 (i.e., when the master tile interrupt register was added to the design) and use that as the basis for the new Xe_HP changes.
Now that we track the hardware IP's release number as well as the version number, we can also properly define DG1 has version "12.10" and replace the has_master_unit_irq feature flag with an IP version test.
Bspec: 50875 Cc: Daniele Spurio Ceraolo daniele.ceraolospurio@intel.com Cc: Stuart Summers stuart.summers@intel.com Signed-off-by: Paulo Zanoni paulo.r.zanoni@intel.com Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com Signed-off-by: Tomasz Lis tomasz.lis@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
So I know DG1 upstream is decidedly non-smooth, but basic infrastructure we've had since forever ...
Why was this prep work not upstreamed earlier with some benign commit message that doesn't mention DG2? There's zero DG2 stuff in here, this could have landed months/years ago even. Bringing this up since right this moment we have an internal chat about trees diverging a bit much.
history isn't linear and this commit, the way it is now, didn't exist 1 month ago, so your timescale is misleading. has_master_unit_irq was what we thought we would need to share as much code as possible.
The biggest reason to fork the irq handler is actually not DG1 nor DG2, but XEHPSDV and without those changes it would basically be a 95% copy of the gen11 handler... for someone not looking to what is in the pipeline, it can be a perfect argument to "consolidate these into a single handler".
Lucas De Marchi