Hi Maxime
On Wed, 8 Jul 2020 at 18:43, Maxime Ripard maxime@cerno.tech wrote:
Since most of the HVS channel is setup in the init function, let's move the gamma setup there too. As this makes the HVS mode_set function empty, let's remove it in the process.
Signed-off-by: Maxime Ripard maxime@cerno.tech
Reviewed-by: Dave Stevenson dave.stevenson@raspberrypi.com
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +- drivers/gpu/drm/vc4/vc4_drv.h | 1 +- drivers/gpu/drm/vc4/vc4_hvs.c | 59 +++++++++-------------------------- drivers/gpu/drm/vc4/vc4_txp.c | 1 +- 4 files changed, 16 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 181d3fd57bc7..284a85b9d7d4 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -379,8 +379,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) { vc4_crtc_config_pv(crtc);
vc4_hvs_mode_set_nofb(crtc);}
static void require_hvs_enabled(struct drm_device *dev) diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 4126506b3a69..dfcc684f5d28 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -904,7 +904,6 @@ int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state); void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state); -void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc); void vc4_hvs_dump_state(struct drm_device *dev); void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel); void vc4_hvs_mask_underrun(struct drm_device *dev, int channel); diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index 78bb1c0b0b76..c7de77afbf0a 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -201,6 +201,8 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc, { struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); unsigned int chan = vc4_crtc_state->assigned_channel;
bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;u32 dispbkgndx; u32 dispctrl; /* Turn on the scaler, which will wait for vstart to start@@ -225,6 +227,20 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |SCALER_DISPBKGND_AUTOHS |((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |(interlace ? SCALER_DISPBKGND_INTERLACE : 0));/* Reload the LUT, since the SRAMs would have been disabled if* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.*/vc4_hvs_lut_load(crtc);return 0;}
@@ -421,49 +437,6 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc, } }
-void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc) -{
struct drm_device *dev = crtc->dev;struct vc4_dev *vc4 = to_vc4_dev(dev);struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);struct drm_display_mode *mode = &crtc->state->adjusted_mode;bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;if (vc4_state->assigned_channel == 2) {u32 dispctrl;u32 dsp3_mux;/** SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to* FIFO X'.* SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.** DSP3 is connected to FIFO2 unless the transposer is* enabled. In this case, FIFO 2 is directly accessed by the* TXP IP, and we need to disable the FIFO2 -> pixelvalve1* route.*/if (vc4_state->feed_txp)dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);elsedsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);dispctrl = HVS_READ(SCALER_DISPCTRL) &~SCALER_DISPCTRL_DSP3_MUX_MASK;HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);}HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),SCALER_DISPBKGND_AUTOHS |((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |(interlace ? SCALER_DISPBKGND_INTERLACE : 0));/* Reload the LUT, since the SRAMs would have been disabled if* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.*/vc4_hvs_lut_load(crtc);-}
void vc4_hvs_mask_underrun(struct drm_device *dev, int channel) { struct vc4_dev *vc4 = to_vc4_dev(dev); diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c index a2380d856000..849dcafbfff1 100644 --- a/drivers/gpu/drm/vc4/vc4_txp.c +++ b/drivers/gpu/drm/vc4/vc4_txp.c @@ -436,7 +436,6 @@ static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = { .atomic_flush = vc4_hvs_atomic_flush, .atomic_enable = vc4_txp_atomic_enable, .atomic_disable = vc4_txp_atomic_disable,
.mode_set_nofb = vc4_hvs_mode_set_nofb,};
static irqreturn_t vc4_txp_interrupt(int irq, void *data)
git-series 0.9.1