Re: [PATCH v9 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding

On Sat, Jun 11, 2022 at 10:14:12PM +0800, Liu Ying wrote:

This patch adds bindings for i.MX8qm/qxp display pixel link.

Signed-off-by: Liu Ying victor.liu@nxp.com

v8->v9:

• Add 'fsl,dc-id' and 'fsl,dc-stream-id' properties. (Laurent)

Why? Isn't the graph sufficient for determining the connections? That's what it is for.

• Drop Rob's R-b tag.

v7->v8:

• No change.

v6->v7:

• No change.

v5->v6:

• No change.

v4->v5:

• No change.

v3->v4:

• No change.

v2->v3:

• Add Rob's R-b tag.

v1->v2:

• Use graph schema. (Laurent)
• Require all four pixel link output ports. (Laurent)
• Mention pixel link is accessed via SCU firmware. (Rob)

.../bridge/fsl,imx8qxp-pixel-link.yaml | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 000000000000..38ecc7926fad --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: Freescale i.MX8qm/qxp Display Pixel Link

+maintainers:

• • Liu Ying victor.liu@nxp.com

+description: |

• The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
• asynchronous linkage between pixel sources(display controller or
• camera module) and pixel consumers(imaging or displays).
• It consists of two distinct functions, a pixel transfer function and a
• control interface. Multiple pixel channels can exist per one control channel.
• This binding documentation is only for pixel links whose pixel sources are
• display controllers.
• The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
• firmware.

+properties:

• compatible:
• enum:

•  - fsl,imx8qm-dc-pixel-link
  

•  - fsl,imx8qxp-dc-pixel-link
  

• fsl,dc-id:
• $ref: /schemas/types.yaml#/definitions/uint8
• description: |

•  u8 value representing the display controller index that the pixel link
  

•  connects to.
  

• fsl,dc-stream-id:
• $ref: /schemas/types.yaml#/definitions/uint8
• description: |

•  u8 value representing the display controller stream index that the pixel
  

•  link connects to.
  

• enum: [0, 1]
• ports:
• $ref: /schemas/graph.yaml#/properties/ports
• properties:

•  port@0:
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: The pixel link input port node from upstream video source.
  

• patternProperties:

•  "^port@[1-4]$":
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: The pixel link output port node to downstream bridge.
  

• required:

•  - port@0
  

•  - port@1
  

•  - port@2
  

•  - port@3
  

•  - port@4
  

+allOf:

• • if:

•  properties:
  

•    compatible:
  

•      contains:
  

•        const: fsl,imx8qxp-dc-pixel-link
  

• then:

•  properties:
  

•    fsl,dc-id:
  

•      const: 0
  

• • if:

•  properties:
  

•    compatible:
  

•      contains:
  

•        const: fsl,imx8qm-dc-pixel-link
  

• then:

•  properties:
  

•    fsl,dc-id:
  

•      enum: [0, 1]
  

+required:

• • compatible
• • fsl,dc-id
• • fsl,dc-stream-id
• • ports

+additionalProperties: false

+examples:

• • |
• dc0-pixel-link0 {

•    compatible = "fsl,imx8qxp-dc-pixel-link";
  

•    fsl,dc-id = /bits/ 8 <0>;
  

•    fsl,dc-stream-id = /bits/ 8 <0>;
  

•    ports {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        /* from dc0 pixel combiner channel0 */
  

•        port@0 {
  

•            reg = <0>;
  

•            dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
  

•                remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
  

Isn't dc0 and link0 here the same information (if you get the port number from the remote end).

Rob