On 2020-05-13 11:28 a.m., Rui Salvaterra wrote:
On Wed, 13 May 2020 at 08:19, Daniel Vetter daniel@ffwll.ch wrote:
i915 is even worse, we manually mess around with clflush. In userspace. So really there's 2 axis for dma memory: coherent vs. non-coherent (which is something the dma-api somewhat exposed), i.e. do you need to clflush or not, and cached vs uncached, i.e. are the PAT entries wc or wb.
So, the PowerPC AGP GART ends up being cached and non-coherent, right (assuming there's no way to set the page attributes MTRR/PAT-style)?
It was uncached when I was using my last-gen PowerBook (until a few years ago), though it's possible that broke since then. I don't remember the details how it's done offhand though.
The only theoretical problem there was that the kernel still had a cacheable mapping of the same memory, and any access via that (e.g. prefetch due to access to a neighbouring page) could trigger a machine check. But I don't remember ever hitting that. Maybe I was just lucky all those years.