Use the newly introduced IOMMU_LLC page protection flag to map GPU buffers. This will make sure that proper stage-1 PTE attributes are set for GPU buffers to use system cache. This also introduces MMU_FEATURE_USE_LLC features bit to check for GPUs supporting LLC and set them in the target specific address space creation, in this case we set them for A6XX GPUs.
Signed-off-by: Sai Prakash Ranjan saiprakash.ranjan@codeaurora.org --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ drivers/gpu/drm/msm/msm_iommu.c | 3 +++ drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ 3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 3c7ad51732bb..23da21b6f0ff 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1266,6 +1266,9 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) return ERR_CAST(mmu); }
+ if (!IS_ERR_OR_NULL(a6xx_gpu->llc_slice)) + mmu->features |= MMU_FEATURE_USE_LLC; + /* * Use the aperture start or SZ_16M, whichever is greater. This will * ensure that we align with the allocated pagetable range while still diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 22ac7c692a81..a329f9836422 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -235,6 +235,9 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, if (iova & BIT_ULL(48)) iova |= GENMASK_ULL(63, 49);
+ if (mmu->features & MMU_FEATURE_USE_LLC) + prot |= IOMMU_LLC; + ret = iommu_map_sgtable(iommu->domain, iova, sgt, prot); WARN_ON(!ret);
diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 61ade89d9e48..efcd1939c98e 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -23,12 +23,16 @@ enum msm_mmu_type { MSM_MMU_IOMMU_PAGETABLE, };
+/* MMU features */ +#define MMU_FEATURE_USE_LLC BIT(0) + struct msm_mmu { const struct msm_mmu_funcs *funcs; struct device *dev; int (*handler)(void *arg, unsigned long iova, int flags); void *arg; enum msm_mmu_type type; + u32 features; };
static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,