On Tue, Sep 7, 2021 at 4:01 AM Christian König ckoenig.leichtzumerken@gmail.com wrote:
Briefly describe what this is all about.
Signed-off-by: Christian König christian.koenig@amd.com
Reviewed-by: Alex Deucher alexander.deucher@amd.com
Documentation/gpu/drm-mm.rst | 3 +++ include/drm/ttm/ttm_caching.h | 17 +++++++++++++++++ 2 files changed, 20 insertions(+)
diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index 6b7717af4f88..f22c9f9a2c0e 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -31,6 +31,9 @@ The Translation Table Manager (TTM) .. kernel-doc:: drivers/gpu/drm/ttm/ttm_module.c :doc: TTM
+.. kernel-doc:: include/drm/ttm/ttm_caching.h
- :internal:
The Graphics Execution Manager (GEM)
diff --git a/include/drm/ttm/ttm_caching.h b/include/drm/ttm/ttm_caching.h index 3c9dd65f5aaf..235a743d90e1 100644 --- a/include/drm/ttm/ttm_caching.h +++ b/include/drm/ttm/ttm_caching.h @@ -27,9 +27,26 @@
#define TTM_NUM_CACHING_TYPES 3
+/**
- enum ttm_caching - CPU caching and BUS snooping behavior.
- */
enum ttm_caching {
/*** @ttm_uncached: Most defensive option for device mappings,* don't even allow write combining.*/ ttm_uncached,/*** @ttm_write_combined: Don't cache read accesses, but allow at least* writes to be combined.*/ ttm_write_combined,/*** @ttm_cached: Fully cached like normal system memory, requires that* devices snoop the CPU cache on accesses.*/ ttm_cached};
-- 2.25.1