On Mon, 2022-06-20 at 11:12 +0800, CK Hu wrote:
On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote:
From: Markus Schneider-Pargmann msp@baylibre.com
This patch adds a embedded displayport driver for the MediaTek mt8195 SoC.
It supports the MT8195, the embedded DisplayPort units. It offers DisplayPort 1.4 with up to 4 lanes.
The driver creates a child device for the phy. The child device will never exist without the parent being active. As they are sharing a register range, the parent passes a regmap pointer to the child so that both can work with the same register range. The phy driver sets device data that is read by the parent to get the phy device that can be used to control the phy properties.
This driver is based on an initial version by Jitao shi jitao.shi@mediatek.com
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Cleanup the drivers and modify comments from reviewers] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
[snip]
+static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp) +{
- u8 target_frame_rate = 60;
- u32 target_pixel_clk;
- struct drm_display_mode mode;
- struct mtk_dp_timings *timings = &mtk_dp->info.timings;
- drm_display_mode_from_videomode(&timings->vm, &mode);
- if (mtk_dp->info.timings.frame_rate > 0) {
target_frame_rate = mtk_dp->info.timings.frame_rate;target_pixel_clk = mode.htotal * mode.vtotal *target_frame_rate;- } else if (mtk_dp->info.timings.pix_rate_khz > 0) {
target_pixel_clk = mtk_dp->info.timings.pix_rate_khz *1000;
- } else {
target_pixel_clk = mode.htotal * mode.vtotal *target_frame_rate;- }
- mtk_dp->info.timings.pix_rate_khz = target_pixel_clk / 1000;
It seems that pix_rate_khz is used only here and does not used in another place, so pix_rate_khz is useless, remove it.
Regards, CK
this variable will be used in audio patch. I will move it to audio patch.
BRs, Bo-Chen
+}