-----Original Message----- From: Nautiyal, Ankit K ankit.k.nautiyal@intel.com Sent: Sunday, November 1, 2020 3:37 PM To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org; Shankar, Uma uma.shankar@intel.com; Kulkarni, Vandita vandita.kulkarni@intel.com; ville.syrjala@linux.intel.com; Sharma, Swati2 swati2.sharma@intel.com Subject: [PATCH v2 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder
This patch adds support to read and store the DSC capabilities of the HDMI2.1 PCon encoder. It also adds a new field to store these caps, The caps are read during dfp update and can later be used to get the PPS parameters for PCON-HDMI2.1 sink pair. Which inturn will be used to take a call to override the existing PPS-metadata, by either writing the entire new PPS metadata, or by writing only the PPS override parameters.
v2: Restructured the code to read all capability DPCDs at once and store in an array in intel_dp structure.
Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com
.../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++++++++++++++++ 2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2c58d63928b8..f43ded030c14 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1309,6 +1309,7 @@ struct intel_dp { u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; u8 fec_capable;
- u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; /* source rates */ int num_source_rates; const int *source_rates;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6177169c4401..2e7ddb062efe 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3869,6 +3869,24 @@ cpt_set_link_train(struct intel_dp *intel_dp, intel_de_posting_read(dev_priv, intel_dp->output_reg); }
+static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) {
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- /* Clear the cached register set to avoid using stale values */
Drop this extra line. With this fixed Reviewed-by: Uma Shankar uma.shankar@intel.com
- memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
intel_dp->pcon_dsc_dpcd,sizeof(intel_dp->pcon_dsc_dpcd)) < 0)drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",DP_PCON_DSC_ENCODER);- drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp-pcon_dsc_dpcd); }
static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp) { int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps; @@ - 6645,6 +6663,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, intel_dp->dfp.max_tmds_clock, intel_dp->dfp.pcon_max_frl_bw, intel_dp->dfp.sink_max_frl_bw);
- intel_dp_get_pcon_dsc_cap(intel_dp);
}
static void
2.17.1