[radeon-alex:amd-staging-drm-next 9963/9999] drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:26: warning: "CC_DRM_ID_STRAPS__ATI_REV_ID_MASK" redefined

23 Jun 2020


      tree:   git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head:   2fecc2a42eb2ca00277fe34dafcf9ece398a848e
commit: 788c2ef8c423ccd8c62a471c7e7debe115b3e124 [9963/9999] drm amdgpu: SI UVD add uvd_v3_1 to makefile
config: x86_64-randconfig-a014-20200623 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
reproduce (this is a W=1 build):
        git checkout 788c2ef8c423ccd8c62a471c7e7debe115b3e124
        # save the attached .config to linux build tree
        make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot lkp@intel.com
All warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:26: warning: "CC_DRM_ID_STRAPS__ATI_REV_ID_MASK" redefined
26 | #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2471: note: this is the location of the previous definition
    2471 | #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK  0xf0000000
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:27: warning: "CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT" redefined
27 | #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2472: note: this is the location of the previous definition
    2472 | #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:744: warning: "IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK" redefined
744 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2345: note: this is the location of the previous definition
    2345 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:760: warning: "IH_RB_WPTR__RB_OVERFLOW_MASK" redefined
760 | #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2344: note: this is the location of the previous definition
    2344 | #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:988: warning: "SRBM_SOFT_RESET__SOFT_RESET_IH_MASK" redefined
988 | #define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2347: note: this is the location of the previous definition
    2347 | #define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1028: warning: "SRBM_STATUS__IH_BUSY_MASK" redefined
1028 | #define SRBM_STATUS__IH_BUSY_MASK 0x00020000L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2346: note: this is the location of the previous definition
    2346 | #define SRBM_STATUS__IH_BUSY_MASK 0x20000
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1032: warning: "SRBM_STATUS__MCB_BUSY_MASK" redefined
1032 | #define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2435: note: this is the location of the previous definition
    2435 | #define SRBM_STATUS__MCB_BUSY_MASK 0x200
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1033: warning: "SRBM_STATUS__MCB_BUSY__SHIFT" redefined
1033 | #define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2436: note: this is the location of the previous definition
    2436 | #define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1034: warning: "SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK" redefined
1034 | #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2437: note: this is the location of the previous definition
    2437 | #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1035: warning: "SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT" redefined
1035 | #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2438: note: this is the location of the previous definition
    2438 | #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1036: warning: "SRBM_STATUS__MCC_BUSY_MASK" redefined
1036 | #define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2439: note: this is the location of the previous definition
    2439 | #define SRBM_STATUS__MCC_BUSY_MASK 0x800
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1037: warning: "SRBM_STATUS__MCC_BUSY__SHIFT" redefined
1037 | #define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2440: note: this is the location of the previous definition
    2440 | #define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1038: warning: "SRBM_STATUS__MCD_BUSY_MASK" redefined
1038 | #define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2441: note: this is the location of the previous definition
    2441 | #define SRBM_STATUS__MCD_BUSY_MASK 0x1000
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1039: warning: "SRBM_STATUS__MCD_BUSY__SHIFT" redefined
1039 | #define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2442: note: this is the location of the previous definition
    2442 | #define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1048: warning: "SRBM_STATUS__VMC_BUSY_MASK" redefined
1048 | #define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2443: note: this is the location of the previous definition
    2443 | #define SRBM_STATUS__VMC_BUSY_MASK 0x100
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:35:
...
...
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:1049: warning: "SRBM_STATUS__VMC_BUSY__SHIFT" redefined
1049 | #define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:29:
   drivers/gpu/drm/amd/amdgpu/sid.h:2444: note: this is the location of the previous definition
    2444 | #define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
         | 
   In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33,
                    from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
                    from drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
                    from drivers/gpu/drm/amd/amdgpu/amdgpu.h:65,
                    from drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c:27:
   drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: 'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
      76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
         |                                ^~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: 'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=]
      75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
         |                                ^~~~~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: 'dc_fixpt_e' defined but not used [-Wunused-const-variable=]
      74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
         |                                ^~~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: 'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
      73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
         |                                ^~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: 'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
      72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
         |                                ^~~~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning: 'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
      67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
         |                                ^~~~~~~~~~~~~
vim +/CC_DRM_ID_STRAPS__ATI_REV_ID_MASK +26 drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h
de2bdb3dcf9228 Tom St Denis 2016-10-26    25  
de2bdb3dcf9228 Tom St Denis 2016-10-26   @26  #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   @27  #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
de2bdb3dcf9228 Tom St Denis 2016-10-26    28  #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
de2bdb3dcf9228 Tom St Denis 2016-10-26    29  #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26    30  #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26    31  #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26    32  #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26    33  #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26    34  #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26    35  #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26    36  #define CLIENT0_BM__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    37  #define CLIENT0_BM__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    38  #define CLIENT0_CD0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    39  #define CLIENT0_CD0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    40  #define CLIENT0_CD1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    41  #define CLIENT0_CD1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    42  #define CLIENT0_CD2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    43  #define CLIENT0_CD2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    44  #define CLIENT0_CD3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    45  #define CLIENT0_CD3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    46  #define CLIENT0_CK0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    47  #define CLIENT0_CK0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    48  #define CLIENT0_CK1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    49  #define CLIENT0_CK1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    50  #define CLIENT0_CK2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    51  #define CLIENT0_CK2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    52  #define CLIENT0_CK3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    53  #define CLIENT0_CK3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    54  #define CLIENT0_K0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    55  #define CLIENT0_K0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    56  #define CLIENT0_K1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    57  #define CLIENT0_K1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    58  #define CLIENT0_K2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    59  #define CLIENT0_K2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    60  #define CLIENT0_K3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    61  #define CLIENT0_K3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    62  #define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    63  #define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    64  #define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    65  #define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    66  #define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    67  #define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    68  #define CLIENT1_BM__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    69  #define CLIENT1_BM__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    70  #define CLIENT1_CD0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    71  #define CLIENT1_CD0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    72  #define CLIENT1_CD1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    73  #define CLIENT1_CD1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    74  #define CLIENT1_CD2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    75  #define CLIENT1_CD2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    76  #define CLIENT1_CD3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    77  #define CLIENT1_CD3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    78  #define CLIENT1_CK0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    79  #define CLIENT1_CK0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    80  #define CLIENT1_CK1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    81  #define CLIENT1_CK1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    82  #define CLIENT1_CK2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    83  #define CLIENT1_CK2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    84  #define CLIENT1_CK3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    85  #define CLIENT1_CK3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    86  #define CLIENT1_K0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    87  #define CLIENT1_K0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    88  #define CLIENT1_K1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    89  #define CLIENT1_K1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    90  #define CLIENT1_K2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    91  #define CLIENT1_K2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    92  #define CLIENT1_K3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    93  #define CLIENT1_K3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    94  #define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    95  #define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    96  #define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    97  #define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26    98  #define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26    99  #define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   100  #define CLIENT2_BM__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   101  #define CLIENT2_BM__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   102  #define CLIENT2_CD0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   103  #define CLIENT2_CD0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   104  #define CLIENT2_CD1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   105  #define CLIENT2_CD1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   106  #define CLIENT2_CD2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   107  #define CLIENT2_CD2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   108  #define CLIENT2_CD3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   109  #define CLIENT2_CD3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   110  #define CLIENT2_CK0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   111  #define CLIENT2_CK0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   112  #define CLIENT2_CK1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   113  #define CLIENT2_CK1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   114  #define CLIENT2_CK2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   115  #define CLIENT2_CK2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   116  #define CLIENT2_CK3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   117  #define CLIENT2_CK3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   118  #define CLIENT2_K0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   119  #define CLIENT2_K0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   120  #define CLIENT2_K1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   121  #define CLIENT2_K1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   122  #define CLIENT2_K2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   123  #define CLIENT2_K2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   124  #define CLIENT2_K3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   125  #define CLIENT2_K3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   126  #define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   127  #define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   128  #define CLIENT2_OFFSET__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   129  #define CLIENT2_OFFSET__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   130  #define CLIENT2_STATUS__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   131  #define CLIENT2_STATUS__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   132  #define CLIENT3_BM__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   133  #define CLIENT3_BM__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   134  #define CLIENT3_CD0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   135  #define CLIENT3_CD0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   136  #define CLIENT3_CD1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   137  #define CLIENT3_CD1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   138  #define CLIENT3_CD2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   139  #define CLIENT3_CD2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   140  #define CLIENT3_CD3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   141  #define CLIENT3_CD3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   142  #define CLIENT3_CK0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   143  #define CLIENT3_CK0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   144  #define CLIENT3_CK1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   145  #define CLIENT3_CK1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   146  #define CLIENT3_CK2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   147  #define CLIENT3_CK2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   148  #define CLIENT3_CK3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   149  #define CLIENT3_CK3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   150  #define CLIENT3_K0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   151  #define CLIENT3_K0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   152  #define CLIENT3_K1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   153  #define CLIENT3_K1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   154  #define CLIENT3_K2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   155  #define CLIENT3_K2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   156  #define CLIENT3_K3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   157  #define CLIENT3_K3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   158  #define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   159  #define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   160  #define CLIENT3_OFFSET__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   161  #define CLIENT3_OFFSET__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   162  #define CLIENT3_STATUS__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   163  #define CLIENT3_STATUS__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   164  #define CP_CONFIG__CP_RDREQ_URG_MASK 0x00000f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   165  #define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   166  #define CP_CONFIG__CP_REQ_TRAN_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   167  #define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   168  #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   169  #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   170  #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0x000000ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   171  #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   172  #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26   173  #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   174  #define DH_TEST__DH_TEST_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   175  #define DH_TEST__DH_TEST__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   176  #define EXP0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   177  #define EXP0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   178  #define EXP1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   179  #define EXP1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   180  #define EXP2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   181  #define EXP2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   182  #define EXP3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   183  #define EXP3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   184  #define EXP4__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   185  #define EXP4__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   186  #define EXP5__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   187  #define EXP5__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   188  #define EXP6__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   189  #define EXP6__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   190  #define EXP7__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   191  #define EXP7__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   192  #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   193  #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   194  #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
de2bdb3dcf9228 Tom St Denis 2016-10-26   195  #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   196  #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   197  #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26   198  #define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   199  #define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   200  #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   201  #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
de2bdb3dcf9228 Tom St Denis 2016-10-26   202  #define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
de2bdb3dcf9228 Tom St Denis 2016-10-26   203  #define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   204  #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   205  #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
de2bdb3dcf9228 Tom St Denis 2016-10-26   206  #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
de2bdb3dcf9228 Tom St Denis 2016-10-26   207  #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   208  #define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   209  #define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
de2bdb3dcf9228 Tom St Denis 2016-10-26   210  #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   211  #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   212  #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   213  #define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   214  #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   215  #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x0000001d
de2bdb3dcf9228 Tom St Denis 2016-10-26   216  #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x00000007L
de2bdb3dcf9228 Tom St Denis 2016-10-26   217  #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   218  #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x00400000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   219  #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x00000016
de2bdb3dcf9228 Tom St Denis 2016-10-26   220  #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x00800000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   221  #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x00000017
de2bdb3dcf9228 Tom St Denis 2016-10-26   222  #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   223  #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x0000001f
de2bdb3dcf9228 Tom St Denis 2016-10-26   224  #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x000001f8L
de2bdb3dcf9228 Tom St Denis 2016-10-26   225  #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   226  #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
de2bdb3dcf9228 Tom St Denis 2016-10-26   227  #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26   228  #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0f000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   229  #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26   230  #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   231  #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   232  #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   233  #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013
de2bdb3dcf9228 Tom St Denis 2016-10-26   234  #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   235  #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x0000001e
de2bdb3dcf9228 Tom St Denis 2016-10-26   236  #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
de2bdb3dcf9228 Tom St Denis 2016-10-26   237  #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   238  #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x0000003fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   239  #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   240  #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   241  #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   242  #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   243  #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   244  #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003cL
de2bdb3dcf9228 Tom St Denis 2016-10-26   245  #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   246  #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   247  #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0x0000000f
de2bdb3dcf9228 Tom St Denis 2016-10-26   248  #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   249  #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0x0000000e
de2bdb3dcf9228 Tom St Denis 2016-10-26   250  #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   251  #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   252  #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26   253  #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   254  #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   255  #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   256  #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26   257  #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   258  #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   259  #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   260  #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26   261  #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   262  #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   263  #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   264  #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
de2bdb3dcf9228 Tom St Denis 2016-10-26   265  #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   266  #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   267  #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   268  #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   269  #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   270  #define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   271  #define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   272  #define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001f80L
de2bdb3dcf9228 Tom St Denis 2016-10-26   273  #define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   274  #define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x0000007eL
de2bdb3dcf9228 Tom St Denis 2016-10-26   275  #define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   276  #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   277  #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   278  #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   279  #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   280  #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   281  #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   282  #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x00000780L
de2bdb3dcf9228 Tom St Denis 2016-10-26   283  #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   284  #define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   285  #define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d
de2bdb3dcf9228 Tom St Denis 2016-10-26   286  #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26   287  #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   288  #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x00001000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   289  #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0x0000000c
de2bdb3dcf9228 Tom St Denis 2016-10-26   290  #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
de2bdb3dcf9228 Tom St Denis 2016-10-26   291  #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   292  #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x00080000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   293  #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x00000013
de2bdb3dcf9228 Tom St Denis 2016-10-26   294  #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
de2bdb3dcf9228 Tom St Denis 2016-10-26   295  #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26   296  #define HDP_MISC_CNTL__VM_ID_MASK 0x0000001eL
de2bdb3dcf9228 Tom St Denis 2016-10-26   297  #define HDP_MISC_CNTL__VM_ID__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   298  #define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   299  #define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   300  #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   301  #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   302  #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x0000001eL
de2bdb3dcf9228 Tom St Denis 2016-10-26   303  #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   304  #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x03000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   305  #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26   306  #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0x00c00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   307  #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x00000016
de2bdb3dcf9228 Tom St Denis 2016-10-26   308  #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x00000060L
de2bdb3dcf9228 Tom St Denis 2016-10-26   309  #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   310  #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0x0c000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   311  #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x0000001a
de2bdb3dcf9228 Tom St Denis 2016-10-26   312  #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x30000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   313  #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x0000001c
de2bdb3dcf9228 Tom St Denis 2016-10-26   314  #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x00300000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   315  #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   316  #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x00000380L
de2bdb3dcf9228 Tom St Denis 2016-10-26   317  #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   318  #define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x00008000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   319  #define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0x0000000f
de2bdb3dcf9228 Tom St Denis 2016-10-26   320  #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x00001c00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   321  #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26   322  #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x00006000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   323  #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0x0000000d
de2bdb3dcf9228 Tom St Denis 2016-10-26   324  #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x40000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   325  #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x0000001e
de2bdb3dcf9228 Tom St Denis 2016-10-26   326  #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   327  #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   328  #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0x000e0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   329  #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x00000011
de2bdb3dcf9228 Tom St Denis 2016-10-26   330  #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   331  #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x0000001b
de2bdb3dcf9228 Tom St Denis 2016-10-26   332  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x00000038L
de2bdb3dcf9228 Tom St Denis 2016-10-26   333  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   334  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0x000ffe00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   335  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   336  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x000001c0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   337  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   338  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x00000007L
de2bdb3dcf9228 Tom St Denis 2016-10-26   339  #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   340  #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x000007ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   341  #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   342  #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800L
de2bdb3dcf9228 Tom St Denis 2016-10-26   343  #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26   344  #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   345  #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   346  #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   347  #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   348  #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   349  #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   350  #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   351  #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   352  #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000ff00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   353  #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   354  #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   355  #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   356  #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x00000007L
de2bdb3dcf9228 Tom St Denis 2016-10-26   357  #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   358  #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x00000018L
de2bdb3dcf9228 Tom St Denis 2016-10-26   359  #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   360  #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   361  #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   362  #define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x00003800L
de2bdb3dcf9228 Tom St Denis 2016-10-26   363  #define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26   364  #define HDP_TILING_CONFIG__BANK_TILING_MASK 0x00000030L
de2bdb3dcf9228 Tom St Denis 2016-10-26   365  #define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   366  #define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0x000000c0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   367  #define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   368  #define HDP_TILING_CONFIG__PIPE_TILING_MASK 0x0000000eL
de2bdb3dcf9228 Tom St Denis 2016-10-26   369  #define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   370  #define HDP_TILING_CONFIG__ROW_TILING_MASK 0x00000700L
de2bdb3dcf9228 Tom St Denis 2016-10-26   371  #define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   372  #define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0x0000c000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   373  #define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0x0000000e
de2bdb3dcf9228 Tom St Denis 2016-10-26   374  #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   375  #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   376  #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000f0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   377  #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   378  #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   379  #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   380  #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000f000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   381  #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0x0000000c
de2bdb3dcf9228 Tom St Denis 2016-10-26   382  #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   383  #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   384  #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00f00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   385  #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   386  #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0f000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   387  #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26   388  #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   389  #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x0000001c
de2bdb3dcf9228 Tom St Denis 2016-10-26   390  #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   391  #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   392  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   393  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   394  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0x00000ff0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   395  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   396  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   397  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0x0000000c
de2bdb3dcf9228 Tom St Denis 2016-10-26   398  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   399  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x0000001e
de2bdb3dcf9228 Tom St Denis 2016-10-26   400  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   401  #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x0000001f
de2bdb3dcf9228 Tom St Denis 2016-10-26   402  #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   403  #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   404  #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000ff00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   405  #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   406  #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00ff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   407  #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   408  #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   409  #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26   410  #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   411  #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   412  #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   413  #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   414  #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   415  #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   416  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   417  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x00000012
de2bdb3dcf9228 Tom St Denis 2016-10-26   418  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   419  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   420  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
de2bdb3dcf9228 Tom St Denis 2016-10-26   421  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   422  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000f0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   423  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   424  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   425  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x00000013
de2bdb3dcf9228 Tom St Denis 2016-10-26   426  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   427  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   428  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   429  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   430  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x00020000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   431  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x00000011
de2bdb3dcf9228 Tom St Denis 2016-10-26   432  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000f800L
de2bdb3dcf9228 Tom St Denis 2016-10-26   433  #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26   434  #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   435  #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   436  #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   437  #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   438  #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   439  #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   440  #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   441  #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   442  #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   443  #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   444  #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   445  #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   446  #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   447  #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   448  #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   449  #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   450  #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   451  #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   452  #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   453  #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   454  #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   455  #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   456  #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   457  #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   458  #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   459  #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   460  #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   461  #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   462  #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   463  #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   464  #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   465  #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   466  #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   467  #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   468  #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   469  #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   470  #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   471  #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   472  #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   473  #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   474  #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   475  #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   476  #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   477  #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   478  #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   479  #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   480  #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   481  #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   482  #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   483  #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   484  #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   485  #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   486  #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   487  #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   488  #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   489  #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   490  #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   491  #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   492  #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   493  #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   494  #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   495  #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   496  #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   497  #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   498  #define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   499  #define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   500  #define HDP_XDP_DBG_ADDR__STS_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   501  #define HDP_XDP_DBG_ADDR__STS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   502  #define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   503  #define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   504  #define HDP_XDP_DBG_DATA__STS_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   505  #define HDP_XDP_DBG_DATA__STS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   506  #define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   507  #define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   508  #define HDP_XDP_DBG_MASK__STS_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   509  #define HDP_XDP_DBG_MASK__STS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   510  #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   511  #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   512  #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   513  #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   514  #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   515  #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   516  #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03ffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   517  #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   518  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   519  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0x0000000c
de2bdb3dcf9228 Tom St Denis 2016-10-26   520  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   521  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0x0000000d
de2bdb3dcf9228 Tom St Denis 2016-10-26   522  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   523  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   524  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000fc0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   525  #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   526  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   527  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   528  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000006L
de2bdb3dcf9228 Tom St Denis 2016-10-26   529  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   530  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26   531  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   532  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x000000f0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   533  #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   534  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   535  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   536  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x00000006L
de2bdb3dcf9228 Tom St Denis 2016-10-26   537  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   538  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26   539  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   540  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x07800000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   541  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x00000017
de2bdb3dcf9228 Tom St Denis 2016-10-26   542  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x00700000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   543  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   544  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26   545  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   546  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x00000060L
de2bdb3dcf9228 Tom St Denis 2016-10-26   547  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   548  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26   549  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   550  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   551  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x0000001b
de2bdb3dcf9228 Tom St Denis 2016-10-26   552  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000fc000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   553  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0x0000000e
de2bdb3dcf9228 Tom St Denis 2016-10-26   554  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x00003f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   555  #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   556  #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   557  #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   558  #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
de2bdb3dcf9228 Tom St Denis 2016-10-26   559  #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   560  #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   561  #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   562  #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   563  #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   564  #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   565  #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   566  #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   567  #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   568  #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   569  #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   570  #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   571  #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   572  #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   573  #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   574  #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   575  #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   576  #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   577  #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   578  #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   579  #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   580  #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   581  #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   582  #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   583  #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   584  #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   585  #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   586  #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   587  #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   588  #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   589  #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   590  #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   591  #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   592  #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   593  #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   594  #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   595  #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   596  #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   597  #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   598  #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   599  #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   600  #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   601  #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   602  #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   603  #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   604  #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000f0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   605  #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   606  #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   607  #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   608  #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   609  #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   610  #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
de2bdb3dcf9228 Tom St Denis 2016-10-26   611  #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   612  #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x01e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   613  #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   614  #define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x001ffffeL
de2bdb3dcf9228 Tom St Denis 2016-10-26   615  #define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   616  #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   617  #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   618  #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x01e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   619  #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   620  #define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x001ffffeL
de2bdb3dcf9228 Tom St Denis 2016-10-26   621  #define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   622  #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   623  #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   624  #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x01e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   625  #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   626  #define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x001ffffeL
de2bdb3dcf9228 Tom St Denis 2016-10-26   627  #define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   628  #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   629  #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   630  #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x01e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   631  #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   632  #define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x001ffffeL
de2bdb3dcf9228 Tom St Denis 2016-10-26   633  #define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   634  #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   635  #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   636  #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x01e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   637  #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   638  #define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x001ffffeL
de2bdb3dcf9228 Tom St Denis 2016-10-26   639  #define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   640  #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   641  #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   642  #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x01e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   643  #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   644  #define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x001ffffeL
de2bdb3dcf9228 Tom St Denis 2016-10-26   645  #define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   646  #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   647  #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   648  #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x01e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   649  #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   650  #define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x001ffffeL
de2bdb3dcf9228 Tom St Denis 2016-10-26   651  #define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   652  #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   653  #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   654  #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x00003fffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   655  #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   656  #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x00000018L
de2bdb3dcf9228 Tom St Denis 2016-10-26   657  #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   658  #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   659  #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   660  #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
de2bdb3dcf9228 Tom St Denis 2016-10-26   661  #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   662  #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x0000003fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   663  #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   664  #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26   665  #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   666  #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26   667  #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   668  #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   669  #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   670  #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   671  #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   672  #define HFS_SEED0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   673  #define HFS_SEED0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   674  #define HFS_SEED1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   675  #define HFS_SEED1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   676  #define HFS_SEED2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   677  #define HFS_SEED2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   678  #define HFS_SEED3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   679  #define HFS_SEED3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   680  #define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0x0000ff00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   681  #define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   682  #define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   683  #define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   684  #define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26   685  #define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   686  #define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x00000007L
de2bdb3dcf9228 Tom St Denis 2016-10-26   687  #define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26   688  #define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   689  #define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   690  #define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x00000300L
de2bdb3dcf9228 Tom St Denis 2016-10-26   691  #define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   692  #define IH_CNTL__ENABLE_INTR_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   693  #define IH_CNTL__ENABLE_INTR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   694  #define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x00007c00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   695  #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26   696  #define IH_CNTL__MC_SWAP_MASK 0x00000006L
de2bdb3dcf9228 Tom St Denis 2016-10-26   697  #define IH_CNTL__MC_SWAP__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   698  #define IH_CNTL__MC_TRAN_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26   699  #define IH_CNTL__MC_TRAN__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   700  #define IH_CNTL__MC_VMID_MASK 0x1e000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   701  #define IH_CNTL__MC_VMID__SHIFT 0x00000019
de2bdb3dcf9228 Tom St Denis 2016-10-26   702  #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   703  #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   704  #define IH_CNTL__MC_WRREQ_CREDIT_MASK 0x000f8000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   705  #define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x0000000f
de2bdb3dcf9228 Tom St Denis 2016-10-26   706  #define IH_CNTL__RPTR_REARM_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26   707  #define IH_CNTL__RPTR_REARM__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   708  #define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26   709  #define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   710  #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   711  #define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   712  #define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x00000004L
de2bdb3dcf9228 Tom St Denis 2016-10-26   713  #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   714  #define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26   715  #define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   716  #define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x00000020L
de2bdb3dcf9228 Tom St Denis 2016-10-26   717  #define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   718  #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   719  #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   720  #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   721  #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   722  #define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   723  #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   724  #define IH_PERFMON_CNTL__CLEAR1_MASK 0x00000200L
de2bdb3dcf9228 Tom St Denis 2016-10-26   725  #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   726  #define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   727  #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   728  #define IH_PERFMON_CNTL__ENABLE1_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26   729  #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   730  #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000000fcL
de2bdb3dcf9228 Tom St Denis 2016-10-26   731  #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   732  #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0000fc00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   733  #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26   734  #define IH_RB_BASE__ADDR_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   735  #define IH_RB_BASE__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   736  #define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   737  #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   738  #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26   739  #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   740  #define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26   741  #define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   742  #define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL
de2bdb3dcf9228 Tom St Denis 2016-10-26   743  #define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   744  #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   745  #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f
de2bdb3dcf9228 Tom St Denis 2016-10-26   746  #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   747  #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   748  #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26   749  #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   750  #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   751  #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   752  #define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL
de2bdb3dcf9228 Tom St Denis 2016-10-26   753  #define IH_RB_RPTR__OFFSET__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   754  #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   755  #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   756  #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL
de2bdb3dcf9228 Tom St Denis 2016-10-26   757  #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   758  #define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL
de2bdb3dcf9228 Tom St Denis 2016-10-26   759  #define IH_RB_WPTR__OFFSET__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   760  #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   761  #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   762  #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L
de2bdb3dcf9228 Tom St Denis 2016-10-26   763  #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26   764  #define IH_STATUS__IDLE_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   765  #define IH_STATUS__IDLE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   766  #define IH_STATUS__INPUT_IDLE_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   767  #define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   768  #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26   769  #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   770  #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L
de2bdb3dcf9228 Tom St Denis 2016-10-26   771  #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   772  #define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26   773  #define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   774  #define IH_STATUS__MC_WR_STALL_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26   775  #define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   776  #define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26   777  #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   778  #define IH_STATUS__RB_FULL_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26   779  #define IH_STATUS__RB_FULL__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   780  #define IH_STATUS__RB_IDLE_MASK 0x00000004L
de2bdb3dcf9228 Tom St Denis 2016-10-26   781  #define IH_STATUS__RB_IDLE__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   782  #define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L
de2bdb3dcf9228 Tom St Denis 2016-10-26   783  #define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   784  #define KEFUSE0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   785  #define KEFUSE0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   786  #define KEFUSE1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   787  #define KEFUSE1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   788  #define KEFUSE2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   789  #define KEFUSE2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   790  #define KEFUSE3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   791  #define KEFUSE3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   792  #define KHFS0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   793  #define KHFS0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   794  #define KHFS1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   795  #define KHFS1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   796  #define KHFS2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   797  #define KHFS2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   798  #define KHFS3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   799  #define KHFS3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   800  #define KSESSION0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   801  #define KSESSION0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   802  #define KSESSION1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   803  #define KSESSION1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   804  #define KSESSION2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   805  #define KSESSION2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   806  #define KSESSION3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   807  #define KSESSION3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   808  #define KSIG0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   809  #define KSIG0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   810  #define KSIG1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   811  #define KSIG1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   812  #define KSIG2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   813  #define KSIG2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   814  #define KSIG3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   815  #define KSIG3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   816  #define LX0__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   817  #define LX0__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   818  #define LX1__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   819  #define LX1__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   820  #define LX2__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   821  #define LX2__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   822  #define LX3__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   823  #define LX3__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   824  #define RINGOSC_MASK__MASK_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   825  #define RINGOSC_MASK__MASK__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   826  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L
de2bdb3dcf9228 Tom St Denis 2016-10-26   827  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   828  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L
de2bdb3dcf9228 Tom St Denis 2016-10-26   829  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26   830  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   831  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   832  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   833  #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   834  #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   835  #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f
de2bdb3dcf9228 Tom St Denis 2016-10-26   836  #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00e00000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   837  #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   838  #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ff00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   839  #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   840  #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0x000000ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   841  #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   842  #define SEM_MAILBOX__HOSTPORT_MASK 0x0000ff00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   843  #define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   844  #define SEM_MAILBOX__SIDEPORT_MASK 0x000000ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   845  #define SEM_MAILBOX__SIDEPORT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   846  #define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L
de2bdb3dcf9228 Tom St Denis 2016-10-26   847  #define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   848  #define SPU_PORT_STATUS__RESERVED_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   849  #define SPU_PORT_STATUS__RESERVED__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   850  #define SRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   851  #define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   852  #define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   853  #define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   854  #define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
de2bdb3dcf9228 Tom St Denis 2016-10-26   855  #define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   856  #define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   857  #define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   858  #define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x00020000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   859  #define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x00000011
de2bdb3dcf9228 Tom St Denis 2016-10-26   860  #define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   861  #define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   862  #define SRBM_CNTL__READ_TIMEOUT_MASK 0x000003ffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   863  #define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   864  #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x0000003fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   865  #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   866  #define SRBM_DEBUG_DATA__DATA_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   867  #define SRBM_DEBUG_DATA__DATA__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   868  #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   869  #define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   870  #define SRBM_DEBUG__IGNORE_RDY_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   871  #define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   872  #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26   873  #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   874  #define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26   875  #define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26   876  #define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26   877  #define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   878  #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000004L
de2bdb3dcf9228 Tom St Denis 2016-10-26   879  #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   880  #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x00000020L
de2bdb3dcf9228 Tom St Denis 2016-10-26   881  #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   882  #define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   883  #define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   884  #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   885  #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x0000001c
de2bdb3dcf9228 Tom St Denis 2016-10-26   886  #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x08000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   887  #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x0000001b
de2bdb3dcf9228 Tom St Denis 2016-10-26   888  #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x04000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   889  #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x0000001a
de2bdb3dcf9228 Tom St Denis 2016-10-26   890  #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x02000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   891  #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x00000019
de2bdb3dcf9228 Tom St Denis 2016-10-26   892  #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x01000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   893  #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26   894  #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x00800000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   895  #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x00000017
de2bdb3dcf9228 Tom St Denis 2016-10-26   896  #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x00400000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   897  #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x00000016
de2bdb3dcf9228 Tom St Denis 2016-10-26   898  #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x00200000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   899  #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26   900  #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   901  #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   902  #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x00080000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   903  #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x00000013
de2bdb3dcf9228 Tom St Denis 2016-10-26   904  #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x00040000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   905  #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x00000012
de2bdb3dcf9228 Tom St Denis 2016-10-26   906  #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x00020000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   907  #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x00000011
de2bdb3dcf9228 Tom St Denis 2016-10-26   908  #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   909  #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26   910  #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x00008000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   911  #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0x0000000f
de2bdb3dcf9228 Tom St Denis 2016-10-26   912  #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x00004000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   913  #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0x0000000e
de2bdb3dcf9228 Tom St Denis 2016-10-26   914  #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x00002000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   915  #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0x0000000d
de2bdb3dcf9228 Tom St Denis 2016-10-26   916  #define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x00001000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   917  #define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0x0000000c
de2bdb3dcf9228 Tom St Denis 2016-10-26   918  #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x00000800L
de2bdb3dcf9228 Tom St Denis 2016-10-26   919  #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26   920  #define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x00000200L
de2bdb3dcf9228 Tom St Denis 2016-10-26   921  #define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   922  #define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   923  #define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x0000001d
de2bdb3dcf9228 Tom St Denis 2016-10-26   924  #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26   925  #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   926  #define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x00000400L
de2bdb3dcf9228 Tom St Denis 2016-10-26   927  #define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26   928  #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26   929  #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   930  #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26   931  #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26   932  #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000020L
de2bdb3dcf9228 Tom St Denis 2016-10-26   933  #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   934  #define SRBM_GFX_CNTL__VMID_MASK 0x000000f0L
de2bdb3dcf9228 Tom St Denis 2016-10-26   935  #define SRBM_GFX_CNTL__VMID__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26   936  #define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   937  #define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   938  #define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   939  #define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   940  #define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L
de2bdb3dcf9228 Tom St Denis 2016-10-26   941  #define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   942  #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26   943  #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   944  #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   945  #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   946  #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   947  #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   948  #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   949  #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   950  #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   951  #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   952  #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   953  #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   954  #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26   955  #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   956  #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   957  #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   958  #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
de2bdb3dcf9228 Tom St Denis 2016-10-26   959  #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   960  #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
de2bdb3dcf9228 Tom St Denis 2016-10-26   961  #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26   962  #define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26   963  #define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26   964  #define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL
de2bdb3dcf9228 Tom St Denis 2016-10-26   965  #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002
de2bdb3dcf9228 Tom St Denis 2016-10-26   966  #define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   967  #define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f
de2bdb3dcf9228 Tom St Denis 2016-10-26   968  #define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x02000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   969  #define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x00000019
de2bdb3dcf9228 Tom St Denis 2016-10-26   970  #define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x01000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   971  #define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26   972  #define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x04000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   973  #define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x0000001a
de2bdb3dcf9228 Tom St Denis 2016-10-26   974  #define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x00400000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   975  #define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x00000016
de2bdb3dcf9228 Tom St Denis 2016-10-26   976  #define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   977  #define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x0000001d
de2bdb3dcf9228 Tom St Denis 2016-10-26   978  #define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x00100000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   979  #define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x00000014
de2bdb3dcf9228 Tom St Denis 2016-10-26   980  #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26   981  #define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26   982  #define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x00000020L
de2bdb3dcf9228 Tom St Denis 2016-10-26   983  #define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26   984  #define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26   985  #define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26   986  #define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x00000200L
de2bdb3dcf9228 Tom St Denis 2016-10-26   987  #define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26   988  #define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L
de2bdb3dcf9228 Tom St Denis 2016-10-26   989  #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26   990  #define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x00000800L
de2bdb3dcf9228 Tom St Denis 2016-10-26   991  #define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26   992  #define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x00800000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   993  #define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x00000017
de2bdb3dcf9228 Tom St Denis 2016-10-26   994  #define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x00400000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   995  #define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x00000016
de2bdb3dcf9228 Tom St Denis 2016-10-26   996  #define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x00004000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   997  #define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0x0000000e
de2bdb3dcf9228 Tom St Denis 2016-10-26   998  #define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x00008000L
de2bdb3dcf9228 Tom St Denis 2016-10-26   999  #define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0x0000000f
de2bdb3dcf9228 Tom St Denis 2016-10-26  1000  #define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x00200000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1001  #define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x00000015
de2bdb3dcf9228 Tom St Denis 2016-10-26  1002  #define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x00040000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1003  #define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x00000012
de2bdb3dcf9228 Tom St Denis 2016-10-26  1004  #define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x01000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1005  #define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x00000018
de2bdb3dcf9228 Tom St Denis 2016-10-26  1006  #define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x00020000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1007  #define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x00000011
de2bdb3dcf9228 Tom St Denis 2016-10-26  1008  #define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x02000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1009  #define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x00000019
de2bdb3dcf9228 Tom St Denis 2016-10-26  1010  #define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x00080000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1011  #define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x00000013
de2bdb3dcf9228 Tom St Denis 2016-10-26  1012  #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1013  #define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26  1014  #define SRBM_STATUS2__VCE_BUSY_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1015  #define SRBM_STATUS2__VCE_BUSY__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26  1016  #define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x00000008L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1017  #define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x00000003
de2bdb3dcf9228 Tom St Denis 2016-10-26  1018  #define SRBM_STATUS2__XDMA_BUSY_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1019  #define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26  1020  #define SRBM_STATUS2__XSP_BUSY_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1021  #define SRBM_STATUS2__XSP_BUSY__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26  1022  #define SRBM_STATUS__BIF_BUSY_MASK 0x20000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1023  #define SRBM_STATUS__BIF_BUSY__SHIFT 0x0000001d
de2bdb3dcf9228 Tom St Denis 2016-10-26  1024  #define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x00000020L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1025  #define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x00000005
de2bdb3dcf9228 Tom St Denis 2016-10-26  1026  #define SRBM_STATUS__HI_RQ_PENDING_MASK 0x00000040L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1027  #define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x00000006
de2bdb3dcf9228 Tom St Denis 2016-10-26  1028  #define SRBM_STATUS__IH_BUSY_MASK 0x00020000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1029  #define SRBM_STATUS__IH_BUSY__SHIFT 0x00000011
de2bdb3dcf9228 Tom St Denis 2016-10-26  1030  #define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x00000080L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1031  #define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x00000007
de2bdb3dcf9228 Tom St Denis 2016-10-26  1032  #define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1033  #define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009
de2bdb3dcf9228 Tom St Denis 2016-10-26  1034  #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1035  #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a
de2bdb3dcf9228 Tom St Denis 2016-10-26  1036  #define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1037  #define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b
de2bdb3dcf9228 Tom St Denis 2016-10-26  1038  #define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1039  #define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c
de2bdb3dcf9228 Tom St Denis 2016-10-26  1040  #define SRBM_STATUS__SEM_BUSY_MASK 0x00004000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1041  #define SRBM_STATUS__SEM_BUSY__SHIFT 0x0000000e
de2bdb3dcf9228 Tom St Denis 2016-10-26  1042  #define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x00000010L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1043  #define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x00000004
de2bdb3dcf9228 Tom St Denis 2016-10-26  1044  #define SRBM_STATUS__UVD_BUSY_MASK 0x00080000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1045  #define SRBM_STATUS__UVD_BUSY__SHIFT 0x00000013
de2bdb3dcf9228 Tom St Denis 2016-10-26  1046  #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x00000002L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1047  #define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x00000001
de2bdb3dcf9228 Tom St Denis 2016-10-26  1048  #define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1049  #define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26  1050  #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1051  #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26  1052  #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26  1053  #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26  1054  #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1055  #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26  1056  #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26  1057  #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26  1058  #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1059  #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26  1060  #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
de2bdb3dcf9228 Tom St Denis 2016-10-26  1061  #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26  1062  #define UVD_CONFIG__UVD_RDREQ_URG_MASK 0x00000f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1063  #define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26  1064  #define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1065  #define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26  1066  #define VCE_CONFIG__VCE_RDREQ_URG_MASK 0x00000f00L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1067  #define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x00000008
de2bdb3dcf9228 Tom St Denis 2016-10-26  1068  #define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x00010000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1069  #define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26  1070  #define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x00080000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1071  #define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x00000013
de2bdb3dcf9228 Tom St Denis 2016-10-26  1072  #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1073  #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x0000001f
de2bdb3dcf9228 Tom St Denis 2016-10-26  1074  #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0x0000ffffL
de2bdb3dcf9228 Tom St Denis 2016-10-26  1075  #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x00000000
de2bdb3dcf9228 Tom St Denis 2016-10-26  1076  #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000L
de2bdb3dcf9228 Tom St Denis 2016-10-26  1077  #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x00000010
de2bdb3dcf9228 Tom St Denis 2016-10-26  1078
:::::: The code at line 26 was first introduced by commit
:::::: de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33 drm/amd/amdgpu: Introduction of SI registers (v2)
:::::: TO: Tom St Denis tom.stdenis@amd.com
:::::: CC: Alex Deucher alexander.deucher@amd.com
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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[radeon-alex:amd-staging-drm-next 9963/9999] drivers/gpu/drm/amd/amdgpu/../include/asic_reg/oss/oss_1_0_sh_mask.h:26: warning: "CC_DRM_ID_STRAPS__ATI_REV_ID_MASK" redefined