15 Jan
2016
15 Jan
'16
3:02 a.m.
On Thu, Jan 14, 2016 at 04:24:49PM +0100, Maxime Ripard wrote:
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
Acked-by: Rob Herring robh@kernel.org
drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-sun4i-pll3.c | 90 +++++++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c