From: Mykola Lysenko Mykola.Lysenko@amd.com
Get on par with buffer management changes made in base driver
Signed-off-by: Mykola Lysenko Mykola.Lysenko@amd.com Acked-by: Harry Wentland harry.wentland@amd.com --- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 10 ++++------ drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 17 +++++++++++------ 2 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c index aeb7887356cd..0ceb505355e8 100644 --- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c @@ -1329,7 +1329,7 @@ void amdgpu_dm_flip_cleanup( } else DRM_ERROR("failed to reserve buffer after flip\n");
- drm_gem_object_unreference_unlocked(&works->old_rbo->gem_base); + amdgpu_bo_unref(&works->old_rbo); kfree(works->shared); kfree(works); } @@ -1379,13 +1379,11 @@ static void dm_page_flip(struct amdgpu_device *adev, target = acrtc->target;
/* - * Received a page flip call after the display has been reset. Make sure - * we return the buffers. + * Received a page flip call after the display has been reset. + * Just return in this case. Everything should be clean-up on reset. */ - if (!target) { - amdgpu_dm_flip_cleanup(adev, acrtc); + if (!target) return; - }
addr.address.grph.addr.low_part = lower_32_bits(crtc_base); addr.address.grph.addr.high_part = upper_32_bits(crtc_base); diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c index da6c0116aa1a..7643f751fcc6 100644 --- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c @@ -1972,22 +1972,27 @@ static void manage_dm_interrupts( struct amdgpu_crtc *acrtc, bool enable) { + /* + * this is not correct translation but will work as soon as VBLANK + * constant is the same as PFLIP + */ + int irq_type = + amdgpu_crtc_idx_to_irq_type( + adev, + acrtc->crtc_id); + if (enable) { drm_crtc_vblank_on(&acrtc->base); amdgpu_irq_get( adev, &adev->pageflip_irq, - amdgpu_crtc_idx_to_irq_type( - adev, - acrtc->crtc_id)); + irq_type); } else { unsigned long flags; amdgpu_irq_put( adev, &adev->pageflip_irq, - amdgpu_crtc_idx_to_irq_type( - adev, - acrtc->crtc_id)); + irq_type); drm_crtc_vblank_off(&acrtc->base);
/*