On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote:
From: Jordan Crouse jcrouse@codeaurora.org
Use the new adreno-smmu-priv fault info function to get more SMMU debug registers and print the current TTBR0 to debug per-instance pagetables and figure out which GPU block generated the request.
Acked-by: Bjorn Andersson bjorn.andersson@linaro.org
Regards, Bjorn
Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 76 +++++++++++++++++++++++++-- drivers/gpu/drm/msm/msm_iommu.c | 11 +++- drivers/gpu/drm/msm/msm_mmu.h | 4 +- 4 files changed, 87 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index f46562c12022..eb030b00bff4 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1075,7 +1075,7 @@ bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return true; }
-static int a5xx_fault_handler(void *arg, unsigned long iova, int flags) +static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) { struct msm_gpu *gpu = arg; pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", @@ -1085,7 +1085,7 @@ static int a5xx_fault_handler(void *arg, unsigned long iova, int flags) gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)), gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));
- return -EFAULT;
- return 0;
}
static void a5xx_cp_err_irq(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c7f0ddb12d8f..fc19db10bff1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1032,18 +1032,88 @@ static void a6xx_recover(struct msm_gpu *gpu) msm_gpu_hw_init(gpu); }
-static int a6xx_fault_handler(void *arg, unsigned long iova, int flags) +static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) +{
- static const char *uche_clients[7] = {
"VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",- };
- u32 val;
- if (mid < 1 || mid > 3)
return "UNKNOWN";- /*
* The source of the data depends on the mid ID read from FSYNR1.* and the client ID read from the UCHE block*/- val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
- /* mid = 3 is most precise and refers to only one block per client */
- if (mid == 3)
return uche_clients[val & 7];- /* For mid=2 the source is TP or VFD except when the client id is 0 */
- if (mid == 2)
return ((val & 7) == 0) ? "TP" : "TP|VFD";- /* For mid=1 just return "UCHE" as a catchall for everything else */
- return "UCHE";
+}
+static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) +{
- if (id == 0)
return "CP";- else if (id == 4)
return "CCU";- else if (id == 6)
return "CDP Prefetch";- return a6xx_uche_fault_block(gpu, id);
+}
+#define ARM_SMMU_FSR_TF BIT(1) +#define ARM_SMMU_FSR_PF BIT(3) +#define ARM_SMMU_FSR_EF BIT(4)
+static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) { struct msm_gpu *gpu = arg;
- struct adreno_smmu_fault_info *info = data;
- const char *type = "UNKNOWN";
- pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
- /*
* Print a default message if we couldn't get the data from the* adreno-smmu-priv*/- if (!info) {
pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n", iova, flags, gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
- return -EFAULT;
return 0;- }
- if (info->fsr & ARM_SMMU_FSR_TF)
type = "TRANSLATION";- else if (info->fsr & ARM_SMMU_FSR_PF)
type = "PERMISSION";- else if (info->fsr & ARM_SMMU_FSR_EF)
type = "EXTERNAL";- pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
info->ttbr0, iova,flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ", type,a6xx_fault_block(gpu, info->fsynr1 & 0xff),gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));- return 0;
}
static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 50d881794758..6975b95c3c29 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -211,8 +211,17 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { struct msm_iommu *iommu = arg;
- struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev);
- struct adreno_smmu_fault_info info, *ptr = NULL;
- if (adreno_smmu->get_fault_info) {
adreno_smmu->get_fault_info(adreno_smmu->cookie, &info);ptr = &info;- }
- if (iommu->base.handler)
return iommu->base.handler(iommu->base.arg, iova, flags);
return iommu->base.handler(iommu->base.arg, iova, flags, ptr);- pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); return 0;
} diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 61ade89d9e48..a88f44c3268d 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -26,7 +26,7 @@ enum msm_mmu_type { struct msm_mmu { const struct msm_mmu_funcs *funcs; struct device *dev;
- int (*handler)(void *arg, unsigned long iova, int flags);
- int (*handler)(void *arg, unsigned long iova, int flags, void *data); void *arg; enum msm_mmu_type type;
}; @@ -43,7 +43,7 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
int (*handler)(void *arg, unsigned long iova, int flags))
int (*handler)(void *arg, unsigned long iova, int flags, void *data)){ mmu->arg = arg; mmu->handler = handler; -- 2.31.1
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