From: Alan Cox alan@linux.intel.com
And update to the actual product naming as the press release is now out.
http://newsroom.intel.com/docs/DOC-2553#pressmaterials
- Fixes the wrong ifdef check - Fixes the missing crtc count declaration
Signed-off-by: Alan Cox alan@linux.intel.com ---
drivers/gpu/drm/gma500/Kconfig | 7 ++++--- drivers/gpu/drm/gma500/cdv_device.c | 3 ++- drivers/gpu/drm/gma500/psb_drv.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig index 78e46e8..978b66f 100644 --- a/drivers/gpu/drm/gma500/Kconfig +++ b/drivers/gpu/drm/gma500/Kconfig @@ -19,8 +19,9 @@ config DRM_GMA600 platforms with LVDS ports. HDMI and MIPI are not currently supported.
-config DRM_CEDARVIEW - bool "Intel Cedarview support (Experimental)" +config DRM_GMA3600 + bool "Intel GMA3600/3650 support (Experimental)" depends on DRM_GMA500 help - Say yes to include support for Intel Cedarview platforms + Say yes to include basic support for Intel GMA3600/3650 (Intel + Cedar Trail) platforms. diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c index 7e8028a..4a5b099 100644 --- a/drivers/gpu/drm/gma500/cdv_device.c +++ b/drivers/gpu/drm/gma500/cdv_device.c @@ -327,9 +327,10 @@ static int cdv_chip_setup(struct drm_device *dev) /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
const struct psb_ops cdv_chip_ops = { - .name = "Cedartrail", + .name = "GMA3600/3650", .accel_2d = 0, .pipes = 2, + .crtcs = 2, .sgx_offset = MRST_SGX_OFFSET, .chip_setup = cdv_chip_setup,
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c index 962b92d..96756cc 100644 --- a/drivers/gpu/drm/gma500/psb_drv.c +++ b/drivers/gpu/drm/gma500/psb_drv.c @@ -64,7 +64,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = { /* Atom E620 */ { 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops}, #endif -#if defined(CONFIG_DRM_CDV) +#if defined(CONFIG_DRM_GMA3600) { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},