On Fri, Oct 08, 2021 at 02:56:25PM -0700, Matt Roper wrote:
From: Paulo Zanoni paulo.r.zanoni@intel.com
We'll be adding multi-tile support soon; on multi-tile platforms interrupts are per-tile and every tile has the full set of interrupt registers.
In this commit we start passing intel_gt instead of dev_priv for the functions that are related to Xe_HP irq handling. Right now we're still passing tile 0 everywhere, but in later patches we'll start actually passing the correct tile.
Signed-off-by: Paulo Zanoni paulo.r.zanoni@intel.com Co-authored-by: Tvrtko Ursulin tvrtko.ursulin@intel.com Signed-off-by: Tvrtko Ursulin tvrtko.ursulin@intel.com Signed-off-by: Radhakrishna Sripada radhakrishna.sripada@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
mostly replacing the i915->uncore with the gt->uncore, which right now should be the same. The other changes are just changing
Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com
Lucas De Marchi