Patch based on a previous series by Shashank Sharma.
v2: Update contributors
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Lionel Landwerlin lionel.g.landwerlin@intel.com Signed-off-by: Kumar, Kiran S kiran.s.kumar@intel.com Signed-off-by: Kausal Malladi kausalmalladi@gmail.com --- drivers/gpu/drm/i915/i915_drv.c | 3 + drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++++ drivers/gpu/drm/i915/intel_color.c | 139 ++++++++++++++++++++++++++++++++++++- 3 files changed, 180 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b65aa20..eb69ff2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -68,6 +68,8 @@ static struct drm_driver driver;
#define BDW_COLORS \ .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } +#define CHV_COLORS \ + .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
static const struct intel_device_info intel_i830_info = { .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, @@ -325,6 +327,7 @@ static const struct intel_device_info intel_cherryview_info = { .display_mmio_offset = VLV_DISPLAY_BASE, GEN_CHV_PIPEOFFSETS, CURSOR_OFFSETS, + CHV_COLORS, };
static const struct intel_device_info intel_skylake_info = { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1dc5d3b..c1e5189 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7685,6 +7685,46 @@ enum skl_disp_power_wells { #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B, _PAL_PREC_GC_MAX_C) + (i) * 4) #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE3(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B, _PAL_PREC_EXT_GC_MAX_C) + (i) * 4)
+/* pipe CSC & degamma/gamma LUTs on CHV */ +#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) +#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) +#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) +#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) +#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) +#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) +#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) +#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) +#define CGM_PIPE_MODE_GAMMA (1 << 2) +#define CGM_PIPE_MODE_CSC (1 << 1) +#define CGM_PIPE_MODE_DEGAMMA (1 << 0) + +#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) +#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) +#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) +#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) +#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) +#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) +#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) +#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) + +#define _CGM_PIPE_C_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x6B900) +#define _CGM_PIPE_C_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x6B904) +#define _CGM_PIPE_C_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x6B908) +#define _CGM_PIPE_C_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6B90C) +#define _CGM_PIPE_C_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x6B910) +#define _CGM_PIPE_C_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000) +#define _CGM_PIPE_C_GAMMA (VLV_DISPLAY_BASE + 0x6B000) +#define _CGM_PIPE_C_MODE (VLV_DISPLAY_BASE + 0x6BA00) + +#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01, _CGM_PIPE_C_CSC_COEFF01) +#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23, _CGM_PIPE_C_CSC_COEFF23) +#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45, _CGM_PIPE_C_CSC_COEFF45) +#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67, _CGM_PIPE_C_CSC_COEFF67) +#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8, _CGM_PIPE_C_CSC_COEFF8) +#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE3(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA, _CGM_PIPE_C_DEGAMMA) + (i) * 4 + (w) * 4) +#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE3(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA, _CGM_PIPE_C_GAMMA) + (i) * 4 + (w) * 4) +#define CGM_PIPE_MODE(pipe) _MMIO_PIPE3(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE, _CGM_PIPE_C_MODE) + /* MIPI DSI registers */
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 782b9d8..da6ff09 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -213,6 +213,54 @@ static void i9xx_load_csc_matrix(struct drm_crtc *crtc) } }
+/* + * Set up the pipe CSC unit on CherryView. + */ +static void cherryview_load_csc_matrix(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_crtc_state *crtc_state = crtc->state; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + + + if (crtc_state->ctm_matrix) { + struct drm_color_ctm *ctm = + (struct drm_color_ctm *)crtc_state->ctm_matrix->data; + uint16_t coeffs[9] = { 0, }; + int i; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { + uint64_t abs_coeff = + ((1ULL << 63) - 1) & ctm->matrix[i]; + + abs_coeff = clamp_val(abs_coeff, 0, (1 << 15) - 1); + + /* Write coefficients in S3.12 format. */ + if (ctm->matrix[i] & (1ULL << 63)) + coeffs[i] = 1 << 15; + coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; + coeffs[i] |= (((abs_coeff >> 19) + 1) >> 1) & 0xfff; + } + + I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), + coeffs[1] << 16 | coeffs[0]); + I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), + coeffs[3] << 16 | coeffs[2]); + I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), + coeffs[5] << 16 | coeffs[4]); + I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), + coeffs[7] << 16 | coeffs[6]); + I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]); + } + + I915_WRITE(CGM_PIPE_MODE(pipe), + (crtc_state->ctm_matrix ? CGM_PIPE_MODE_CSC : 0) | + (crtc_state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | + (crtc_state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0)); +} + /** Loads the legacy palette/gamma unit for the CRTC with the prepared * values. */ @@ -282,6 +330,47 @@ static void broadwell_load_degamma_lut(struct drm_crtc *crtc) I915_WRITE(PREC_PAL_INDEX(pipe), 0); }
+static void cherryview_load_degamma_lut(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc_state *state = crtc->state; + enum pipe pipe = to_intel_crtc(crtc)->pipe; + + if (state->degamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *) state->degamma_lut->data; + uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size; + uint32_t word0, word1; + + for (i = 0; i < lut_size; i++) { + /* Write LUT in U0.14 format. */ + word0 = + (drm_color_lut_extract(lut[i].green, 14) << 16) | + drm_color_lut_extract(lut[i].blue, 14); + word1 = drm_color_lut_extract(lut[i].red, 14); + + I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0); + I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1); + } + /* Write the 65's entry of the LUT with the last entry given + * by user space to clamp values > 1.0. + */ + word0 = + (drm_color_lut_extract(lut[lut_size - 1].green, 14) << 16) | + drm_color_lut_extract(lut[lut_size - 1].blue, 14); + word1 = drm_color_lut_extract(lut[lut_size - 1].red, 14); + + I915_WRITE(CGM_PIPE_DEGAMMA(pipe, lut_size, 0), word0); + I915_WRITE(CGM_PIPE_DEGAMMA(pipe, lut_size, 1), word1); + } + + I915_WRITE(CGM_PIPE_MODE(pipe), + (state->ctm_matrix ? CGM_PIPE_MODE_CSC : 0) | + (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | + (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0)); +} + static void broadwell_load_gamma_lut(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -339,6 +428,47 @@ static void broadwell_load_gamma_lut(struct drm_crtc *crtc) I915_WRITE(PREC_PAL_INDEX(pipe), 0); }
+static void cherryview_load_gamma_lut(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc_state *state = crtc->state; + enum pipe pipe = to_intel_crtc(crtc)->pipe; + + if (state->gamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *) state->gamma_lut->data; + uint32_t i, lut_size = INTEL_INFO(dev)->color.gamma_lut_size; + uint32_t word0, word1; + + for (i = 0; i < lut_size; i++) { + /* Write LUT in U0.10 format. */ + word0 = + (drm_color_lut_extract(lut[i].green, 10) << 16) | + drm_color_lut_extract(lut[i].blue, 10); + word1 = drm_color_lut_extract(lut[i].red, 10); + + I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0); + I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1); + } + /* Write the 257's entry of the LUT with the last entry given + * by user space to clamp values > 1.0. + */ + word0 = + (drm_color_lut_extract(lut[lut_size - 1].green, 10) << 16) | + drm_color_lut_extract(lut[lut_size - 1].blue, 10); + word1 = drm_color_lut_extract(lut[lut_size - 1].red, 10); + + I915_WRITE(CGM_PIPE_GAMMA(pipe, lut_size, 0), word0); + I915_WRITE(CGM_PIPE_GAMMA(pipe, lut_size, 1), word1); + } + + I915_WRITE(CGM_PIPE_MODE(pipe), + (state->ctm_matrix ? CGM_PIPE_MODE_CSC : 0) | + (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | + (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0)); +} + static void intel_color_load_luts_internal(struct drm_crtc *crtc, bool legacy) { @@ -430,8 +560,13 @@ void intel_color_init(struct drm_crtc *crtc) intel_crtc->lut_b[i] = i; }
- if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) || - IS_BROXTON(dev) || IS_KABYLAKE(dev)) { + if (IS_CHERRYVIEW(dev)) { + dev_priv->display.load_degamma_lut = + cherryview_load_degamma_lut; + dev_priv->display.load_gamma_lut = cherryview_load_gamma_lut; + dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix; + } else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) || + IS_BROXTON(dev) || IS_KABYLAKE(dev)) { dev_priv->display.load_degamma_lut = broadwell_load_degamma_lut; dev_priv->display.load_gamma_lut = broadwell_load_gamma_lut; dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;