Set the suitable bits in DP_TP_CTL to stop bit correction when DSC is disabled.
v2: - rebased. - Add additional check for compression state. (Gaurav)
v3: rebased.
v4: - Move the code to the proper spot according to spec (Ville) - Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
Cc: dri-devel@lists.freedesktop.org Cc: Gaurav K Singh gaurav.k.singh@intel.com Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Ville Syrjala ville.syrjala@linux.intel.com Cc: Manasi Navare manasi.d.navare@intel.com Signed-off-by: Anusha Srivatsa anusha.srivatsa@intel.com --- drivers/gpu/drm/i915/intel_ddi.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 807edba4cd6f..5e915c771953 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2925,6 +2925,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, DRM_ERROR("Timed out waiting for FEC Enable Status\n"); }
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum port port = encoder->port; + u32 val; + + if (!crtc_state->fec_enable) + return; + + val = I915_READ(DP_TP_CTL(port)); + val &= ~DP_TP_CTL_FEC_ENABLE; + I915_WRITE(DP_TP_CTL(port), val); + POSTING_READ(DP_TP_CTL(port)); +} + static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -3063,7 +3079,9 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder, static void intel_disable_ddi_buf(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_crtc_state *crtc_state; enum port port = encoder->port; + bool wait = false; u32 val;
@@ -3079,6 +3097,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder) val |= DP_TP_CTL_LINK_TRAIN_PAT1; I915_WRITE(DP_TP_CTL(port), val);
+ /* Disable FEC in DP Sink */ + intel_ddi_disable_fec_state(encoder, crtc_state); + if (wait) intel_wait_ddi_buf_idle(dev_priv, port); }