26 Apr
2017
26 Apr
'17
5:01 p.m.
Linus Walleij linus.walleij@linaro.org writes:
On Mon, Apr 24, 2017 at 9:45 PM, Eric Anholt eric@anholt.net wrote:
This is required for the panel to work on bcm911360, where CLCDCLK is the fixed 200Mhz AXI41 clock. The rate set is still passed up to the CLCDCLK, for platforms that have a settable rate on that one.
Signed-off-by: Eric Anholt eric@anholt.net
I like this, it is pretty.
An aside, for anyone else considering common clk and thinking "this is a bit more complicated than I need": It's really nice for platform debugging to have your divider or mux or whatever show up in /debug/clk/clk_summary. I don't know how many times I've been saved by diffing that file between a good and bad state of my platform.