From: Izhar Ameer Shaikh izhar.ameer.shaikh@xilinx.com
Latching of AIE NPI Interrupts is present in Versal ES1 Silicon Rev, however it has been removed from ES2 rev. As a result on ES1, in order to use the interrupt, a client needs to request PMC to clear/ack the interrupt.
Provide an EEMI IOCTL to serve the same purpose. Note that, this will only be applicable for ES1 rev. For ES2 and other non-silicon platforms, this call will essentially be a NOP in the firmware.
Signed-off-by: Izhar Ameer Shaikh izhar.ameer.shaikh@xilinx.com Signed-off-by: Wendy Liang wendy.liang@xilinx.com --- drivers/firmware/xilinx/zynqmp.c | 14 ++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 22 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index efb8a66..7a0c6a3 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -702,6 +702,20 @@ int zynqmp_pm_set_boot_health_status(u32 value) }
/** + * zynqmp_pm_clear_aie_npi_isr - Clear AI engine NPI interrupt status register + * @node: AI engine node id + * @irq_mask: Mask of AI engine NPI interrupt bit to clear + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_AIE_ISR_CLEAR, + irq_mask, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_clear_aie_npi_isr); + +/** * zynqmp_pm_reset_assert - Request setting of reset (1 - assert, 0 - release) * @reset: Reset to be configured * @assert_flag: Flag stating should reset be asserted (1) or diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 5968df8..b929d57 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -116,6 +116,8 @@ enum pm_ioctl_id { IOCTL_READ_PGGS = 15, /* Set healthy bit value */ IOCTL_SET_BOOT_HEALTH_STATUS = 17, + /* AI engine NPI ISR clear */ + IOCTL_AIE_ISR_CLEAR = 24, };
enum pm_query_id { @@ -357,6 +359,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value); int zynqmp_pm_read_pggs(u32 index, u32 *value); int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); int zynqmp_pm_set_boot_health_status(u32 value); +int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { @@ -507,6 +510,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value) { return -ENODEV; } + +static int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask) +{ + return -ENODEV; +} #endif
#endif /* __FIRMWARE_ZYNQMP_H__ */