Enable accelerated moves and clearing on DG2. On such HW we have minimum page size restrictions when accessing LMEM from the GTT, where we now have to use 64K GTT pages or larger. With the ppGTT the page-table also has a slightly different layout from past generations when using the 64K GTT mode(which is still enabled on via some PDE bit), where it is now compacted down to 32 qword entries. Note that on discrete the paging structures must also be placed in LMEM, and we need to able to modify them via the GTT itself(see patch 3), which is one of the complications here.
v2: Add missing cover letter v3: - Add some r-b tags - Drop the GTT_MAPPABLE approach. We can instead simply pass along the required size/alignment using alloc_pt(). v4: - Drop already merged patches, and add some r-b tags - Add some better docs to patch 3
Matthew Auld (3): drm/i915/gtt: allow overriding the pt alignment drm/i915/gtt: add xehpsdv_ppgtt_insert_entry drm/i915/migrate: add acceleration support for DG2
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 50 +++++- drivers/gpu/drm/i915/gt/intel_gtt.h | 10 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 209 +++++++++++++++++++----- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 16 +- 4 files changed, 239 insertions(+), 46 deletions(-)