On 09/06/2021 00:59, Chun-Jie Chen wrote:
On Mon, 2021-04-12 at 22:04 +0800, Yongqiang Niu wrote:
mt8192 has different routing registers than mt8183
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com
drivers/soc/mediatek/mt8192-mmsys.h | 68 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 7 ++++ 2 files changed, 75 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h new file mode 100644 index 0000000..3179029 --- /dev/null +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H +#define __SOC_MEDIATEK_MT8192_MMSYS_H
+#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 +#define MT8192_DISP_AAL0_SEL_IN 0xf38 +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c +#define MT8192_DISP_DSI0_SEL_IN 0xf40 +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
+#define MT8192_DISP_OVL0_GO_BLEND BIT(0) +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) +#define MT8192_DISP_OVL0_GO_BG BIT(1) +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 +#define MT8192_RDMA0_SOUT_COLOR0 0x1 +#define MT8192_CCORR0_SOUT_AAL0 0x1 +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 +#define MT8192_DSI0_SEL_IN_DITHER0 0x1
+static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
- {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,MT8192_DISP_OVL0_2L_MOUT_EN,MT8192_OVL0_MOUT_EN_DISP_RDMA0,
- }, {
DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,MT8192_DISP_OVL2_2L_MOUT_EN,MT8192_OVL2_2L_MOUT_EN_RDMA4
- }, {
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,MT8192_DISP_DITHER0_MOUT_EN,MT8192_DITHER0_MOUT_IN_DSI0
- }, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L- }, {
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0- }, {
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0- }, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0- }, {
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0- }, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,- }, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,- }
+};
+#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 79e5515..c755617 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -12,6 +12,7 @@
#include "mtk-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8192-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -45,6 +46,12 @@ .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), };
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
- .clk_driver = "clk-mt8192-mm",
- .routes = mmsys_mt8192_routing_table,
- .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
+};
struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data;
Hi Yongqiang,
There is 8192 mmsys compatible data in [1], but seems to lack of it in this patch, because mm clock driver will be bound to platform device in mtk_mmsys_probe.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-1...
Yes, you should add a match in of_match_mtk_mmsys[] for the compatbile. The clock driver should be implemented as a platform device.
Regards, Matthias