Only GPU that has larger SMMU region size (0x8000 dwords) is A530. All other GPUs have 0x4000 SMMU region. However those GPUs work correctly with larger range protected because there is no known registers after SMMU region. This patch needs to be backported to stable releases because A540 GPU was forgotten to get its branch (that would set up protected region of 0x4000 dwords).
Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support") Signed-off-by: Vladimir Lypak vladimir.lypak@gmail.com --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 5e2750eb3810..ecf6318a247f 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -851,11 +851,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* UCHE */ gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16));
- if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) || - adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu) || - adreno_is_a530(adreno_gpu)) - gpu_write(gpu, REG_A5XX_CP_PROTECT(17), - ADRENO_PROTECT_RW(0x10000, 0x8000)); + /* SMMU */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(17), ADRENO_PROTECT_RW(0x10000, 0x8000));
gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); /*