Let's use the newly-added nvmem_cell_read_variable_le_u32() to future proof ourselves a little bit.
Signed-off-by: Douglas Anderson dianders@chromium.org --- This is based on my previous patch ("drm/msm: Fix speed-bin support not to access outside valid memory") which has already landed in msm-next. In case it's not obvious, this patch has a strong dependency on my previous patch and also on patch #1 in this series.
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0e2024defd79..e34705d17559 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1351,17 +1351,16 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, { struct opp_table *opp_table; u32 supp_hw = UINT_MAX; - u16 speedbin; + u32 speedbin; int ret;
- ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin); + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", &speedbin); if (ret) { DRM_DEV_ERROR(dev, "failed to read speed-bin (%d). Some OPPs may not be supported by hardware", ret); goto done; } - speedbin = le16_to_cpu(speedbin);
supp_hw = fuse_to_supp_hw(dev, revn, speedbin);