Hi,
I have a Thinkpad T440s (Haswell) connected to two additional Monitors via a Docking Station (MST).
During Bootup all three displays work, even when X is started. However, if the laptop display is turned off once (either because of power saving, or via xrandr), it fails to "come back". That is if I try to re-enable it the Display stays blank. I believe this used to work in 3.17.
Here is the xrandr Ouput of the edp, when its enabled (but staying blank): Screen 0: minimum 8 x 8, current 3840 x 1200, maximum 32767 x 32767 eDP1 connected 1920x1080+0+0 (normal left inverted right x axis y axis) 309mm x 175mm 1920x1080 60.0*+ 59.9
here is the debug output, while trying to enable it:
[ 416.314290] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 416.314294] [drm:intel_crtc_set_config] [CRTC:12] [FB:149] #connectors=1 (x y) (0 0) [ 416.314299] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 416.314303] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=1 [ 416.314305] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 416.314309] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:12] [ 416.314312] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-3] to [CRTC:8] [ 416.314315] [drm:intel_modeset_stage_output_state] [CONNECTOR:43:DP-4] to [CRTC:16] [ 416.314317] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 416.314321] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 416.314325] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 416.314329] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 416.314332] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18 [ 416.314337] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz [ 416.314341] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18 [ 416.314343] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000 [ 416.314347] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1 [ 416.314351] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B [ 416.314353] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 416.314355] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1 [ 416.314359] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 416.314363] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64 [ 416.314392] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 416.314406] [drm:intel_dump_pipe_config] requested mode: [ 416.314422] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9 [ 416.314435] [drm:intel_dump_pipe_config] adjusted mode: [ 416.314453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9 [ 416.314468] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9 [ 416.314482] [drm:intel_dump_pipe_config] port clock: 270000 [ 416.314496] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 416.314510] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 416.314521] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 416.314524] [drm:intel_dump_pipe_config] ips: 0 [ 416.314527] [drm:intel_dump_pipe_config] double wide: 0 [ 416.314568] [drm:intel_edp_panel_on] Turn eDP power on [ 416.314575] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 416.314585] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008 [ 416.314591] [drm:wait_panel_status] Wait complete [ 416.314599] [drm:wait_panel_on] Wait for panel power on [ 416.314606] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b [ 416.522545] [drm:wait_panel_status] Wait complete [ 416.523689] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 416.524311] [drm:intel_dp_start_link_train] clock recovery OK [ 416.525224] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 416.525528] [drm:intel_edp_backlight_on] [ 416.525533] [drm:intel_panel_enable_backlight] pipe B [ 416.525541] [drm:intel_panel_actually_set_backlight] set backlight PWM = 10 [ 416.530518] [drm:intel_edp_psr_match_conditions] PSR disable by flag [ 416.538553] [drm:ironlake_update_primary_plane] Writing base 030B0000 00000000 0 0 15360 [ 416.538575] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 416.538584] [drm:intel_connector_check_state] [CONNECTOR:39:DP-3] [ 416.538587] [drm:intel_connector_check_state] [CONNECTOR:43:DP-4] [ 416.538590] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 416.538594] [drm:check_encoder_state] [ENCODER:26:TMDS-26] [ 416.538597] [drm:check_encoder_state] [ENCODER:28:DP MST-28] [ 416.538599] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 416.538602] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 416.538604] [drm:check_encoder_state] [ENCODER:33:TMDS-33] [ 416.538607] [drm:check_encoder_state] [ENCODER:35:DP MST-35] [ 416.538610] [drm:check_encoder_state] [ENCODER:36:DP MST-36] [ 416.538612] [drm:check_encoder_state] [ENCODER:37:DP MST-37] [ 416.538615] [drm:check_crtc_state] [CRTC:8] [ 416.538626] [drm:check_crtc_state] [CRTC:12] [ 416.538636] [drm:check_crtc_state] [CRTC:16] [ 416.538646] [drm:check_shared_dpll_state] WRPLL 1 [ 416.538649] [drm:check_shared_dpll_state] WRPLL 2 [ 416.538699] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=851/851 [ 416.538702] [drm:intel_panel_actually_set_backlight] set backlight PWM = 851 [ 416.538835] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=851/851 [ 416.538840] [drm:intel_panel_actually_set_backlight] set backlight PWM = 851 [ 416.538848] [drm:intel_edp_backlight_power] panel power control backlight disable [ 416.742563] [drm:add_framebuffer_internal] [FB:156] [ 419.195100] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [ 419.195112] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
I'm happy to provide further input.
Best Regards Arnd