In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with pixelvalves each being assigned to a given output, but each output can then be muxed to feed from multiple FIFOs.
Since vc4 had that entirely static, both were probably equivalent, but since that changes, let's rename hvs_channel to hvs_output in the vc4_crtc_data, since a pixelvalve is really connected to an output, and not to a FIFO.
Signed-off-by: Maxime Ripard maxime@cerno.tech --- drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++----- drivers/gpu/drm/vc4/vc4_drv.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index d58f881649d5..14e3a962d8a7 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -1056,7 +1056,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { };
static const struct vc4_crtc_data bcm2835_pv0_data = { - .hvs_channel = 0, + .hvs_output = 0, .debugfs_name = "crtc0_regs", .pixels_per_clock = 1, .encoder_types = { @@ -1066,7 +1066,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = { };
static const struct vc4_crtc_data bcm2835_pv1_data = { - .hvs_channel = 2, + .hvs_output = 2, .debugfs_name = "crtc1_regs", .pixels_per_clock = 1, .encoder_types = { @@ -1076,7 +1076,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = { };
static const struct vc4_crtc_data bcm2835_pv2_data = { - .hvs_channel = 1, + .hvs_output = 1, .debugfs_name = "crtc2_regs", .pixels_per_clock = 1, .encoder_types = { @@ -1105,7 +1105,7 @@ static void vc4_set_crtc_possible_masks(struct drm_device *drm, int i;
/* HVS FIFO2 can feed the TXP IP. */ - if (crtc_data->hvs_channel == 2 && + if (crtc_data->hvs_output == 2 && encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { encoder->possible_crtcs |= drm_crtc_mask(crtc); continue; @@ -1167,7 +1167,7 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, &vc4_crtc_funcs, NULL); drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); - vc4_crtc->channel = vc4_crtc->data->hvs_channel; + vc4_crtc->channel = vc4_crtc->data->hvs_output; drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 6c4b78b71446..9d120aae4af9 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -450,8 +450,8 @@ to_vc4_encoder(struct drm_encoder *encoder) }
struct vc4_crtc_data { - /* Which channel of the HVS this pixelvalve sources from. */ - int hvs_channel; + /* Which output of the HVS this pixelvalve sources from. */ + int hvs_output;
/* Number of pixels output per clock period */ u8 pixels_per_clock;