On Fri, 5 Feb 2016 10:39:15 +0100 Maxime Ripard maxime.ripard@free-electrons.com wrote:
+CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-display-clk", sun6i_display_setup);
Please use the display driver from my DRM serie, it covers everything you need here.
If you give me a pointer, I will have a look.
+CLK_OF_DECLARE(sun6i_pll3, "allwinner,sun6i-pll3-clk", sun6i_pll3_setup);
And please use the clk-factors code here.
I don't see how I can get direct 297MHz and 270MHz in fractional mode with that code.