Gen9+ platforms allow CRTC's to be programmed with a background/canvas color below the programmable planes. Let's expose this for use by compositors.
v2: - Split out bgcolor sanitization and programming of csc/gamma bits to a separate patch that we can land before the ABI changes are ready to go in. (Ville) - Change a temporary variable name to be more consistent with other similar functions. (Ville) - Change register name to SKL_CANVAS for consistency with the CHV_CANVAS register.
v3: - Switch register name back to SKL_BOTTOM_COLOR. (Ville) - Use non-_FW register write. (Ville) - Minor parameter rename for consistency. (Ville)
v4: - Removed use of bgcolor_changed flag.
v5: - s/uint64_t/u64/
v6: - Rebase onto latest drm-tip (bgcolor writing now moves to the new color_commit function added by Ville's series)
v7: - Rebase
Cc: dri-devel@lists.freedesktop.org Cc: wei.c.li@intel.com Cc: harish.krupo.kps@intel.com Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++++++ 3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 9ab34902663e..f93153ffc843 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -481,12 +481,17 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; + u64 propval = crtc_state->base.bgcolor; u32 val = 0;
+ /* Hardware is programmed with 10 bits of precision */ + val = DRM_ARGB_RED(propval, 10) << 20 + | DRM_ARGB_GREEN(propval, 10) << 10 + | DRM_ARGB_BLUE(propval, 10); + /* - * We don't (yet) allow userspace to control the pipe background color, - * so force it to black, but apply pipe gamma and CSC appropriately - * so that its handling will match how we program our planes. + * Apply pipe gamma and CSC appropriately so that its handling will + * match how we program our planes. */ if (crtc_state->gamma_enable) val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bbe088b9d057..78e64c62f34f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -11833,8 +11833,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc, { struct intel_crtc *crtc = to_intel_crtc(_crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_atomic_state *state = + to_intel_atomic_state(_crtc_state->state); struct intel_crtc_state *crtc_state = to_intel_crtc_state(_crtc_state); + struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); int ret; bool mode_changed = needs_modeset(crtc_state);
@@ -11864,6 +11868,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc, return ret; }
+ if (crtc_state->base.bgcolor != old_crtc_state->base.bgcolor) + crtc_state->base.color_mgmt_changed = true; + ret = 0; if (dev_priv->display.compute_pipe_wm) { ret = dev_priv->display.compute_pipe_wm(crtc_state); @@ -15210,6 +15217,9 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
+ if (INTEL_GEN(dev_priv) >= 9) + drm_crtc_add_bgcolor_property(&intel_crtc->base); + return 0;
fail: @@ -16495,6 +16505,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ /* Always force bgcolor to solid black */ + crtc_state->base.bgcolor = drm_argb(16, 0xFFFF, 0, 0, 0); + /* Clear any frame start delays used for debugging left by the BIOS */ if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) { i915_reg_t reg = PIPECONF(cpu_transcoder); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fec9fb7cc384..ccb08b759b89 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2773,6 +2773,15 @@ static int i915_display_info(struct seq_file *m, void *unused) intel_plane_info(m, crtc); }
+ if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) { + u64 background = pipe_config->base.bgcolor; + + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n", + DRM_ARGB_RED(background, 10), + DRM_ARGB_GREEN(background, 10), + DRM_ARGB_BLUE(background, 10)); + } + seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", yesno(!crtc->cpu_fifo_underrun_disabled), yesno(!crtc->pch_fifo_underrun_disabled));