On Tue, Mar 21, 2017 at 04:17:00PM -0400, Sean Paul wrote:
On Fri, Mar 17, 2017 at 11:54:22AM +0800, Chris Zhong wrote:
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock.
Signed-off-by: Chris Zhong zyw@rock-chips.com
Changes in v3: None Changes in v2: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 188f6f7..7e17a60 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -10,7 +10,7 @@ Required properties:
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's pll reference clock(ref) and APB clock(pclk). For RK3399, a phy config clock
- (phy_cfg) is additional required. As described in [1].
- (phy_cfg) and a grf clock(grf) are additional required. As described in [1].
These are only required for rk3399, you should make that clear.
I completely missed "For RK3399" on my first pass, sigh. Sorry for the reading comprehension fail.
Minor nit if you want: s/additional// && s/. As/, as/
Either way,
Reviewed-by: Sean Paul seanpaul@chromium.org
Sean
Sean
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2]. For vopb,set the reg = <0> and set the reg = <1> for vopl.
-- 2.6.3
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-- Sean Paul, Software Engineer, Google / Chromium OS