Hi Laurent,
On Thu, Jun 06, 2019 at 07:58:57PM +0300, Laurent Pinchart wrote:
Hi Jacopo,
Thank you for the patch.
On Thu, Jun 06, 2019 at 04:22:05PM +0200, Jacopo Mondi wrote:
Add clock definitions for CMM units on Renesas R-Car Gen3 H3.
Signed-off-by: Jacopo Mondi jacopo+renesas@jmondi.org
drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 86842c9fd314..e8f1d5ec0455 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -200,6 +200,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
- DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
- DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
- DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
- DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
Could you try to get confirmation that S2D1 is the right parent (for all SoCs) ? Apart from that,
It's not.. for r8a7799x it's S1D1, the same parent as the DU clock. The patches in the BSP use the same clocks I have used here, so I assume at least that part is correct.
Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com
Thanks j
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
-- Regards,
Laurent Pinchart