Hi Linus,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-exynos/exynos-drm-next] [also build test ERROR on v5.4 next-20191202] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Linus-Walleij/drm-mcde-Fix-vertical... base: https://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git exynos-drm-next config: nds32-allyesconfig (attached as .config) compiler: nds32le-linux-gcc (GCC) 8.1.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=8.1.0 make.cross ARCH=nds32
If you fix the issue, kindly add following tag Reported-by: kbuild test robot lkp@intel.com
All errors (new ones prefixed by >>):
drivers/gpu/drm/mcde/mcde_dsi.c: In function 'mcde_dsi_setup_video_mode':
drivers/gpu/drm/mcde/mcde_dsi.c:420:2: error: implicit declaration of function 'writel_dsi'; did you mean 'writesl'? [-Werror=implicit-function-declaration]
writel_dsi(d, val, DSI_VID_MAIN_CTL); ^~~~~~~~~~ writesl cc1: some warnings being treated as errors
vim +420 drivers/gpu/drm/mcde/mcde_dsi.c
364 365 static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, 366 const struct drm_display_mode *mode) 367 { 368 u8 bpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format); 369 u64 bpl; 370 u32 hfp; 371 u32 hbp; 372 u32 hsa; 373 u32 blkline_pck, line_duration; 374 u32 blkeol_pck, blkeol_duration; 375 u32 val; 376 377 val = 0; 378 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 379 val |= DSI_VID_MAIN_CTL_BURST_MODE; 380 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 381 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE; 382 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL; 383 } 384 /* RGB header and pixel mode */ 385 switch (d->mdsi->format) { 386 case MIPI_DSI_FMT_RGB565: 387 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 << 388 DSI_VID_MAIN_CTL_HEADER_SHIFT; 389 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS; 390 break; 391 case MIPI_DSI_FMT_RGB666_PACKED: 392 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 << 393 DSI_VID_MAIN_CTL_HEADER_SHIFT; 394 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS; 395 break; 396 case MIPI_DSI_FMT_RGB666: 397 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18 398 << DSI_VID_MAIN_CTL_HEADER_SHIFT; 399 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE; 400 break; 401 case MIPI_DSI_FMT_RGB888: 402 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 << 403 DSI_VID_MAIN_CTL_HEADER_SHIFT; 404 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS; 405 break; 406 default: 407 dev_err(d->dev, "unknown pixel mode\n"); 408 return; 409 } 410 411 /* TODO: TVG could be enabled here */ 412 413 /* Send blanking packet */ 414 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0; 415 /* Send EOL packet */ 416 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0; 417 /* Recovery mode 1 */ 418 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT; 419 /* All other fields zero */
420 writel_dsi(d, val, DSI_VID_MAIN_CTL);
421 422 /* Vertical frame parameters are pretty straight-forward */ 423 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT; 424 /* vertical front porch */ 425 val |= (mode->vsync_start - mode->vdisplay) 426 << DSI_VID_VSIZE_VFP_LENGTH_SHIFT; 427 /* vertical sync active */ 428 val |= (mode->vsync_end - mode->vsync_start) 429 << DSI_VID_VSIZE_VSA_LENGTH_SHIFT; 430 /* vertical back porch */ 431 val |= (mode->vtotal - mode->vsync_end) 432 << DSI_VID_VSIZE_VBP_LENGTH_SHIFT; 433 writel(val, d->regs + DSI_VID_VSIZE); 434 435 /* 436 * Horizontal frame parameters: 437 * horizontal resolution is given in pixels and must be re-calculated 438 * into bytes since this is what the hardware expects. 439 * 440 * 6 + 2 is HFP header + checksum 441 */ 442 hfp = (mode->hsync_start - mode->hdisplay) * bpp - 6 - 2; 443 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 444 /* 445 * 6 is HBP header + checksum 446 * 4 is RGB header + checksum 447 */ 448 hbp = (mode->htotal - mode->hsync_end) * bpp - 4 - 6; 449 /* 450 * 6 is HBP header + checksum 451 * 4 is HSW packet bytes 452 * 4 is RGB header + checksum 453 */ 454 hsa = (mode->hsync_end - mode->hsync_start) * bpp - 4 - 4 - 6; 455 } else { 456 /* 457 * HBP includes both back porch and sync 458 * 6 is HBP header + checksum 459 * 4 is HSW packet bytes 460 * 4 is RGB header + checksum 461 */ 462 hbp = (mode->htotal - mode->hsync_start) * bpp - 4 - 4 - 6; 463 /* HSA is not considered in this mode and set to 0 */ 464 hsa = 0; 465 } 466 dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u\n", 467 hfp, hbp, hsa); 468 469 /* Frame parameters: horizontal sync active */ 470 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT; 471 /* horizontal back porch */ 472 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT; 473 /* horizontal front porch */ 474 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT; 475 writel(val, d->regs + DSI_VID_HSIZE1); 476 477 /* RGB data length (bytes on one scanline) */ 478 val = mode->hdisplay * (bpp / 8); 479 writel(val, d->regs + DSI_VID_HSIZE2); 480 481 /* TODO: further adjustments for TVG mode here */ 482 483 /* 484 * EOL packet length from bits per line calculations: pixel clock 485 * is given in kHz, calculate the time between two pixels in 486 * picoseconds. 487 */ 488 bpl = mode->clock * mode->htotal; 489 bpl *= (d->hs_freq / 8); 490 do_div(bpl, 1000000); /* microseconds */ 491 do_div(bpl, 1000000); /* seconds */ 492 bpl *= d->mdsi->lanes; 493 dev_dbg(d->dev, "calculated bytes per line: %llu\n", bpl); 494 /* 495 * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes 496 * 4 is short packet for vsync/hsync 497 */ 498 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 499 /* Fixme: isn't the hsync width in pixels? */ 500 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6; 501 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT; 502 writel(val, d->regs + DSI_VID_BLKSIZE2); 503 } else { 504 blkline_pck = bpl - 4 - 6; 505 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT; 506 writel(val, d->regs + DSI_VID_BLKSIZE1); 507 } 508 509 line_duration = (blkline_pck + 6) / d->mdsi->lanes; 510 dev_dbg(d->dev, "line duration %u\n", line_duration); 511 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT; 512 /* 513 * This is the time to perform LP->HS on D-PHY 514 * FIXME: nowhere to get this from: DT property on the DSI? 515 */ 516 val |= 0 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT; 517 writel(val, d->regs + DSI_VID_DPHY_TIME); 518 519 /* Calculate block end of line */ 520 blkeol_pck = bpl - mode->hdisplay * bpp - 6; 521 blkeol_duration = (blkeol_pck + 6) / d->mdsi->lanes; 522 dev_dbg(d->dev, "blkeol pck: %u, duration: %u\n", 523 blkeol_pck, blkeol_duration); 524 525 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 526 /* Set up EOL clock for burst mode */ 527 val = readl(d->regs + DSI_VID_BLKSIZE1); 528 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT; 529 writel(val, d->regs + DSI_VID_BLKSIZE1); 530 writel(blkeol_pck, d->regs + DSI_VID_VCA_SETTING2); 531 532 writel(blkeol_duration, d->regs + DSI_VID_PCK_TIME); 533 writel(blkeol_duration - 6, d->regs + DSI_VID_VCA_SETTING1); 534 } 535 536 /* Maximum line limit */ 537 val = readl(d->regs + DSI_VID_VCA_SETTING2); 538 val |= blkline_pck << 539 DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT; 540 writel(val, d->regs + DSI_VID_VCA_SETTING2); 541 542 /* Put IF1 into video mode */ 543 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 544 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE; 545 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 546 547 /* Disable command mode on IF1 */ 548 val = readl(d->regs + DSI_CMD_MODE_CTL); 549 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN; 550 writel(val, d->regs + DSI_CMD_MODE_CTL); 551 552 /* Enable some error interrupts */ 553 val = readl(d->regs + DSI_VID_MODE_STS_CTL); 554 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; 555 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; 556 writel(val, d->regs + DSI_VID_MODE_STS_CTL); 557 558 /* Enable video mode */ 559 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 560 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; 561 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 562 } 563
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