Re: [PATCH v3 1/6] drm/rockchip/dsi: Define and use macros for PHY register addresses

On Wed, Oct 25, 2017 at 11:50:58AM +0800, Nickey Yang wrote:

Replace the hardcoded register address numerical values with macros to clarify the code.

Signed-off-by: Nickey Yang nickey.yang@rock-chips.com

Reviewed-by: Sean Paul seanpaul@chromium.org

---

drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 129 ++++++++++++++++++++++----------- 1 file changed, 85 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index b15755b..95ce253 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -254,6 +254,28 @@ #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) #define DW_MIPI_NEEDS_GRF_CLK BIT(1)

+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 +#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 +#define PLL_LPF_AND_CP_CONTROL 0x12 +#define PLL_INPUT_DIVIDER_RATIO 0x17 +#define PLL_LOOP_DIVIDER_RATIO 0x18 +#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 +#define BANDGAP_AND_BIAS_CONTROL 0x20 +#define TERMINATION_RESISTER_CONTROL 0x21 +#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 +#define HS_RX_CONTROL_OF_LANE_0 0x44 +#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 +#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 +#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 +#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 +#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 +#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 +#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 +#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 +#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 +#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 +#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74

enum { BANDGAP_97_07, BANDGAP_98_05, @@ -447,53 +469,72 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) return ret; }

• dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |

• 			 VCO_RANGE_CON_SEL(vco) |
  

• 			 VCO_IN_CAP_CON_LOW |
  

• 			 REF_BIAS_CUR_SEL);
  

• dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
• dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |

• 			 LPF_RESISTORS_20_KOHM);
  

• dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
• dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
• dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |

• 			 LOW_PROGRAM_EN);
  

• dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |

• 			 HIGH_PROGRAM_EN);
  

• dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
• dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |

• 			 BIASEXTR_SEL(BIASEXTR_127_7));
  

• dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |

• 			 BANDGAP_SEL(BANDGAP_96_10));
  

• dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |

• 			 BIAS_BLOCK_ON | BANDGAP_ON);
  

• dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |

• 			 SETRD_MAX | TER_RESISTORS_ON);
  

• dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |

• 			 SETRD_MAX | POWER_MANAGE |
  

• 			 TER_RESISTORS_ON);
  

• dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
• dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
• dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
• dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
• dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
• dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
• dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
• dw_mipi_dsi_phy_write(dsi, 0x71,

• dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,

• 	      BYPASS_VCO_RANGE |
  

• 	      VCO_RANGE_CON_SEL(vco) |
  

• 	      VCO_IN_CAP_CON_LOW |
  

• 	      REF_BIAS_CUR_SEL);
  

• dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,

• 	      CP_CURRENT_3MA);
  

• dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,

• 	      CP_PROGRAM_EN | LPF_PROGRAM_EN |
  

• 	      LPF_RESISTORS_20_KOHM);
  

• dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,

• 	      HSFREQRANGE_SEL(testdin));
  

• dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,

• 	      INPUT_DIVIDER(dsi->input_div));
  

• dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,

• 	      LOOP_DIV_LOW_SEL(dsi->feedback_div) |
  

• 	      LOW_PROGRAM_EN);
  

• dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,

• 	      LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
  

• 	      HIGH_PROGRAM_EN);
  

• dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,

• 	      PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
  

• dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,

• 	      LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
  

• dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,

• 	      HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
  

• dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,

• 	      POWER_CONTROL | INTERNAL_REG_CURRENT |
  

• 	      BIAS_BLOCK_ON | BANDGAP_ON);
  

• dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,

• 	      TER_RESISTOR_LOW | TER_CAL_DONE |
  

• 	      SETRD_MAX | TER_RESISTORS_ON);
  

• dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,

• 	      TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
  

• 	      SETRD_MAX | POWER_MANAGE |
  

• 	      TER_RESISTORS_ON);
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,

• 	      TLP_PROGRAM_EN | ns2bc(dsi, 500));
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,

• 	      THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,

• 	      THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,

• 	      THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,

• 	      BIT(5) | ns2bc(dsi, 100));
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,

• 	      BIT(5) | (ns2bc(dsi, 60) + 7));
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,

• 	      TLP_PROGRAM_EN | ns2bc(dsi, 500));
  

• dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5));

• dw_mipi_dsi_phy_write(dsi, 0x72,

• dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));

• dw_mipi_dsi_phy_write(dsi, 0x73,

• dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));

• dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100));

• dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,

• 	      BIT(5) | ns2bc(dsi, 100));
  
  

  dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ);

-- 1.9.1