On Tue, Mar 13, 2018 at 06:54:37PM +0100, Giulio Benetti wrote:
Handle both positive and negative dclk polarity, according to bus_flags, taking care of this:
On A20 and similar SoCs, the only way to achieve Positive Edge (Rising Edge), is setting dclk clock phase to 2/3(240°). By default TCON works in Negative Edge(Falling Edge), this is why phase is set to 0 in that case. Unfortunately there's no way to logically invert dclk through IO_POL register. The only acceptable way to work, triple checked with scope, is using clock phase set to 0° for Negative Edge and set to 240° for Positive Edge. On A33 and similar SoCs there would be a 90° phase option, but it divides also dclk by 2. This patch is a way to avoid quirks all around TCON and DOTCLOCK drivers for using A33 90° phase divided by 2 and consequently increase code complexity.
Signed-off-by: Giulio Benetti giulio.benetti@micronovasrl.com
Applied, thanks! Maxime