No functional change. Just reuse the already existing val variable to setup the register. This is in preparation for adding the new feature to reverse the CHA/CHB lane orders. Without this change this call gets very unreadable.
Signed-off-by: Marco Felsch m.felsch@pengutronix.de --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index 2831f0813c3a..112fea004c8e 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -437,11 +437,12 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
regmap_write(ctx->regmap, REG_LVDS_FMT, val); regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); - regmap_write(ctx->regmap, REG_LVDS_LANE, - (ctx->lvds_dual_link_even_odd_swap ? - REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | - REG_LVDS_LANE_CHA_LVDS_TERM | - REG_LVDS_LANE_CHB_LVDS_TERM); + + val = REG_LVDS_LANE_CHA_LVDS_TERM | REG_LVDS_LANE_CHB_LVDS_TERM; + if (ctx->lvds_dual_link_even_odd_swap) + val |= REG_LVDS_LANE_EVEN_ODD_SWAP; + + regmap_write(ctx->regmap, REG_LVDS_LANE, val); regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
le16val = cpu_to_le16(mode->hdisplay);