The SDI encoder modifies the pixel clock of the requested video mode to take the limitations of the PLL into account in the .enable() operation. This should be performed in the .check_timings() operation instead. Move the fixup.
Signed-off-by: Laurent Pinchart laurent.pinchart@ideasonboard.com Reviewed-by: Sebastian Reichel sebastian.reichel@collabora.co.uk --- drivers/gpu/drm/omapdrm/dss/sdi.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/sdi.c b/drivers/gpu/drm/omapdrm/dss/sdi.c index 736a74db3ad5..e98c1b6e3d2d 100644 --- a/drivers/gpu/drm/omapdrm/dss/sdi.c +++ b/drivers/gpu/drm/omapdrm/dss/sdi.c @@ -132,10 +132,8 @@ static void sdi_config_lcd_manager(struct sdi_device *sdi) static int sdi_display_enable(struct omap_dss_device *dssdev) { struct sdi_device *sdi = dssdev_to_sdi(dssdev); - struct videomode *vm = &sdi->vm; - unsigned long fck; struct dispc_clock_info dispc_cinfo; - unsigned long pck; + unsigned long fck; int r;
if (!sdi->output.dispc_channel_connected) { @@ -151,23 +149,13 @@ static int sdi_display_enable(struct omap_dss_device *dssdev) if (r) goto err_get_dispc;
- r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo); + r = sdi_calc_clock_div(sdi, sdi->vm.pixelclock, &fck, &dispc_cinfo); if (r) goto err_calc_clock_div;
sdi->mgr_config.clock_info = dispc_cinfo;
- pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; - - if (pck != vm->pixelclock) { - DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", - vm->pixelclock, pck); - - vm->pixelclock = pck; - } - - - dss_mgr_set_timings(&sdi->output, vm); + dss_mgr_set_timings(&sdi->output, &sdi->vm);
r = dss_set_fck_rate(sdi->dss, fck); if (r) @@ -237,9 +225,28 @@ static void sdi_set_timings(struct omap_dss_device *dssdev, static int sdi_check_timings(struct omap_dss_device *dssdev, struct videomode *vm) { + struct sdi_device *sdi = dssdev_to_sdi(dssdev); + struct dispc_clock_info dispc_cinfo; + unsigned long fck; + unsigned long pck; + int r; + if (vm->pixelclock == 0) return -EINVAL;
+ r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo); + if (r) + return r; + + pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; + + if (pck != vm->pixelclock) { + DSSWARN("Pixel clock adjusted from %lu Hz to %lu Hz\n", + vm->pixelclock, pck); + + vm->pixelclock = pck; + } + return 0; }