Dear Daniel,
On Thu, 19 Mar 2015 01:13:21 +0000 Daniel Stone daniel@fooishbar.org wrote:
Hi Hyungwon,
On 19 March 2015 at 01:02, Hyungwon Hwang human.hwang@samsung.com wrote:
/** The input PLL clock for MIPI DSI in Exynos5433 seemsto be fixed
* by OSC CLK.*/fin = 24 * MHZ;Er, is this always true on other platforms as well? Shouldn't this be a part of the DeviceTree description?
I forgot to change the comment in development. Finally it is found that all exynos mipi dsi's fin is OSC clk which is 24 MHz. So I will remove the comment, but remain the code as it is.
Fair enough. Should pll_clk be removed from the DT description then, if it's fixed to the oscillator?
Yes. It is redundant to represent pll_clk in DT, and it should be removed.
Thanks for your review. I will send it again with the changes you suggested.
Thanks very much!
Cheers, Daniel
Best regards, Hyungwon Hwang