On Wed, Jun 4, 2014 at 9:29 AM, Christian König deathsimple@vodafone.de wrote:
From: Christian König christian.koenig@amd.com
When we set the valid bit on invalid GART entries they are loaded into the TLB when an adjacent entry is loaded. This poisons the TLB with invalid entries which are sometimes not correctly removed on TLB flush.
For stable inclusion the patch probably needs to be modified a bit.
Signed-off-by: Christian König christian.koenig@amd.com Cc: stable@vger.kernel.org
Series is: Reviewed-by: Alex Deucher alexander.deucher@amd.com
stable cc on patch 2 or 3 as well? I suppose we'd need to modify the patches anyway so that they would apply on older kernels anyway.
Alex
drivers/gpu/drm/radeon/rs600.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 0a8be63..e0465b2 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -634,7 +634,10 @@ int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) return -EINVAL; } addr = addr & 0xFFFFFFFFFFFFF000ULL;
addr |= R600_PTE_GART;
if (addr == rdev->dummy_page.addr)addr |= R600_PTE_SYSTEM | R600_PTE_SNOOPED;elseaddr |= R600_PTE_GART; writeq(addr, ptr + (i * 8)); return 0;}
1.9.1