Quoting Kieran Bingham (2022-03-07 17:59:54)
From: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com
Despite the SN65DSI86 being an eDP bridge, on some systems its output is routed to a DisplayPort connector. Enable DisplayPort mode when the next component in the display pipeline is detected as a DisplayPort connector, and disable eDP features in that case.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com Reworked to set bridge type based on the next bridge/connector. Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com -- Changes since v1/RFC:
- Rebased on top of "drm/bridge: ti-sn65dsi86: switch to devm_drm_of_get_bridge"
- eDP/DP mode determined from the next bridge connector type.
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 29f5f7123ed9..461f963faa0b 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -60,6 +60,7 @@ #define SN_LN_ASSIGN_REG 0x59 #define LN_ASSIGN_WIDTH 2 #define SN_ENH_FRAME_REG 0x5A +#define ASSR_CONTROL BIT(0) #define VSTREAM_ENABLE BIT(3) #define LN_POLRS_OFFSET 4 #define LN_POLRS_MASK 0xf0 @@ -91,6 +92,8 @@ #define SN_DATARATE_CONFIG_REG 0x94 #define DP_DATARATE_MASK GENMASK(7, 5) #define DP_DATARATE(x) ((x) << 5) +#define SN_TRAINING_SETTING_REG 0x95 +#define SCRAMBLE_DISABLE BIT(4) #define SN_ML_TX_MODE_REG 0x96 #define ML_TX_MAIN_LINK_OFF 0 #define ML_TX_NORMAL_MODE BIT(0) @@ -1005,6 +1008,11 @@ static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
/* For DisplayPort, use the standard DP scrambler seed. */if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort)regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG,ASSR_CONTROL, 0);/* enable DP PLL */ regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);@@ -1016,6 +1024,11 @@ static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, goto exit; }
/* For DisplayPort, disable scrambling mode. */if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort)regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);/* * We'll try to link train several times. As part of link training * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If@@ -1260,7 +1273,8 @@ static int ti_sn_bridge_probe(struct auxiliary_device *adev, pdata->bridge.funcs = &ti_sn_bridge_funcs; pdata->bridge.of_node = np; pdata->bridge.ops = DRM_BRIDGE_OP_EDID;
pdata->bridge.type = DRM_MODE_CONNECTOR_eDP;
pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
Anyone know if there's any expectation of other types here? Or is it just as safe to do:
pdata->bridge.type = pdata->next_bridge->type;
To achieve the same effect?
-- Kieran
drm_bridge_add(&pdata->bridge);-- 2.32.0