On Wed, 2017-03-08 at 12:13 +0100, Lucas Stach wrote:
The Prefetch Resolve Engine is a prefetch and tile resolve engine which prefetches display data from DRAM to an internal SRAM region. It has a single clock for configuration register access and the functional units. A single shared interrupt is used for status and error signaling.
The only external dependency is the SRAM region to use for the prefetch double buffer.
Signed-off-by: Lucas Stach l.stach@pengutronix.de
I have picked up this series. Rob, are you ok with the bindings in this patch? If so, I'll include it in the next pull request.
regards Philipp
v2:
- change SRAM phandle to "fsl,iram", as used in other imx DT bindings
- drop leading 0 in example
.../bindings/display/imx/fsl-imx-drm.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 971c3eedb1c7..70ae5335d1e3 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -53,6 +53,32 @@ ipu: ipu@18000000 { }; };
+Freescale i.MX PRE (Prefetch Resolve Engine) +============================================
+Required properties: +- compatible: should be "fsl,imx6qp-pre" +- reg: should be register base and length as documented in the
- datasheet
+- clocks : phandle to the PRE axi clock input, as described
- in Documentation/devicetree/bindings/clock/clock-bindings.txt and
- Documentation/devicetree/bindings/clock/imx6q-clock.txt.
+- clock-names: should be "axi" +- interrupts: should contain the PRE interrupt +- fsl,iram: phandle pointing to the mmio-sram device node, that should be
- used for the PRE SRAM double buffer.
+example:
+pre@21c8000 {
- compatible = "fsl,imx6qp-pre";
- reg = <0x021c8000 0x1000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clks IMX6QDL_CLK_PRE0>;
- clock-names = "axi";
- fsl,iram = <&ocram2>;
+};
Parallel display support