Hi Sam,
On Fri, May 13, 2022 at 01:05:06PM +0200, Sam Ravnborg wrote:
On Thu, May 12, 2022 at 07:23:13PM +0530, Venkateshwar Rao Gannavarapu wrote:
The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video data from AXI-4 stream interface.
It supports upto 4 lanes, optional register interface for the DPHY and multiple RGB color formats. This is a MIPI-DSI host driver and provides DSI bus for panels. This driver also helps to communicate with its panel using panel framework.
Thanks for submitting this driver. I have added a few comments in the following that I hope you will find useful to improve the driver.
Signed-off-by: Venkateshwar Rao Gannavarapu venkateshwar.rao.gannavarapu@xilinx.com
drivers/gpu/drm/xlnx/Kconfig | 14 ++ drivers/gpu/drm/xlnx/Makefile | 1 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 456 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 471 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c
[snip]
diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c new file mode 100644 index 0000000..a5291f3 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c
[snip]
+static inline void xlnx_dsi_writel(void __iomem *base, int offset, u32 val) +{
- writel(val, base + offset);
+}
+static inline u32 xlnx_dsi_readl(void __iomem *base, int offset) +{
- return readl(base + offset);
+}
When I see implementations like this I wonder if a regmap would be beneficial?
regmap often seems overkill to me when the driver only needs plain 32-bit mmio read/write, given the overhead it adds at runtime. Is it just me ?
[snip]