On 30/09/2019 18:10, Adam Ford wrote:
On Mon, Sep 30, 2019 at 9:27 AM Tomi Valkeinen tomi.valkeinen@ti.com wrote:
On 30/09/2019 17:20, Tomi Valkeinen wrote:
Let's see what Tero says, but yeah, something is odd here. I expected the max divider to be 16 with Tero's patch, but I don't see it having that effect. I can get the div to 31.
You can see this from the clock register 0x48004e40 (CM_CLKSEL_DSS). The lowest bits are the divider, 5 to 0. The TRM says max div is 32.
Tero said for him the dividers > 16 didn't "stick" to the register. I'm now wondering if he has an old beagleboard with OMAP34xx, which has max div 16.
So testing a bit more here, I can see the DSS working fine and fps as expected when I write values directly to CM_CLKSEL_DSS:5:0, with dividers up to 31. With 32, DSS breaks. The TRM (AM/DM37x) says value 32 is valid.
I wonder if it's somehow being masked with bits 4:0 instead of 5:0 which could potentially make the divider 0 and that value doesn't appear to be valid.
Hmmh, after some testing, it seems there is bad stuff happening with the divider clock implementation, I am re-working it as of now. Basically what is wrong is that with a divider max value of say 16, the driver attempts to craft the max value into a mask, but this ends up being 0x1f. If the max value is 15, it ends up into 0xf which is correct.
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