HDCP2.2 registers offsets on HDMI are defined along with it constants. And also timeout macros for HDCP2.2 adaptation for HDMI is defined.
Signed-off-by: Ramalingam C ramalingam.c@intel.com --- include/drm/drm_hdcp.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index 47862a7..dac9831 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -43,6 +43,42 @@ struct wired_rep_send_ack; struct wired_rep_stream_ready;
/** + * Definitions for HDCP2.2 adaptation for HDMI + */ + +#define DRM_HDCP_2_2_DDC_ADDR (0x74>>1) + +/* HDCP2.2 TIMEOUTs in mSec */ +#define HDCP_2_2_CERT_TIMEOUT 100 +#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT 1000 +#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT 200 +#define HDCP_2_2_PAIRING_TIMEOUT 200 +#define HDCP_2_2_HDMI_LPRIME_TIMEOUT 20 +#define HDCP_2_2_RECVID_LIST_TIMEOUT 3000 +#define HDCP_2_2_STREAM_READY_TIMEOUT 100 + +/* HDCP2.2 Register Offsets */ +#define HDMI_HDCP2_REG_VER_OFFSET 0x50 +#define HDMI_HDCP2_REG_WR_MSG_OFFSET 0x60 +#define HDMI_HDCP2_REG_RXSTATUS_OFFSET 0x70 +#define HDMI_HDCP2_REG_RD_MSG_OFFSET 0x80 +#define HDMI_HDCP2_REG_DBG_OFFSET 0xC0 + +#define HDMI_HDCP_2_2_SUPPORT_MASK (1<<2) + +union rx_status_hdmi { + struct { + uint8_t msg_sz_hi:2; + uint8_t ready:1; + uint8_t reauth_req:1; + uint8_t reserved:4; + uint8_t msg_sz_lo; + } fields; + uint16_t val; +} __packed; + + +/** * HDCP Software stack specific */ /* Bit mask for HDCP spec ver support */