This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Reviewed-by: Rob Herring robh@kernel.org Signed-off-by: Liu Ying victor.liu@nxp.com --- v7->v8: * No change.
v6->v7: * No change.
v5->v6: * No change.
v4->v5: * No change.
v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag.
v2->v3: * No change.
v1->v2: * Use new dt binding way to add clocks in the example.
.../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml new file mode 100644 index 00000000..3ff46e0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-prg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Gasket + +maintainers: + - Liu Ying victor.liu@nxp.com + +description: | + The i.MX8qm/qxp Prefetch Resolve Gasket (PRG) is a gasket interface between + RTRAM controller and Display Controller. The main function is to convert + the AXI interface to the RTRAM interface, which includes re-mapping the + ARADDR to a RTRAM address. + +properties: + compatible: + enum: + - fsl,imx8qxp-prg + - fsl,imx8qm-prg + + reg: + maxItems: 1 + + clocks: + items: + - description: rtram clock + - description: apb clock + + clock-names: + items: + - const: rtram + - const: apb + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + prg@56040000 { + compatible = "fsl,imx8qxp-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg IMX_LPCG_CLK_0>, + <&dc0_prg0_lpcg IMX_LPCG_CLK_4>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + };