On Fri, Dec 17, 2021 at 05:43:20PM +0100, Thierry Reding wrote:
From: Thierry Reding treding@nvidia.com
Convert the Tegra host1x controller bindings from the free-form text format to json-schema.
This also adds the missing display-hub DT bindings that were not previously documented.
Signed-off-by: Thierry Reding treding@nvidia.com
Changes in v4:
- add interconnect, interconnect-names, operating-points-v2 and power-domains property to match latest DT updates
- drop stale reference to DPAUX pad controller bindings
- include dsi-controller.yaml and drop $nodename, #address-cells, #size-cells and patternProperties from DSI bindings
- integrate #sound-dai-cells addition from published patch
- drop some generic, useless comments
Changes in v3:
- split into separate YAML files for simplicity
- add display-hub DT bindings
Changes in v2:
- use additionalProperties instead of unevaluatedProperties where sufficient
- drop redundant $ref and add missing maxItems properties
- drop documentation for standard properties
- remove status properties from example
- drop spurious comments
Hi Rob,
for your convenience, I'm attaching the diff from yesterday's version 3 to make it hopefully a bit easier to review.
Thierry
From f016de415f8a6bf263337bc88a840093a3f7514f Mon Sep 17 00:00:00 2001 From: Thierry Reding treding@nvidia.com Date: Fri, 17 Dec 2021 14:44:47 +0100 Subject: [PATCH] squash! dt-bindings: display: tegra: Convert to json-schema
--- .../display/tegra/nvidia,tegra124-sor.yaml | 3 - .../display/tegra/nvidia,tegra20-dc.yaml | 7 ++ .../display/tegra/nvidia,tegra20-dsi.yaml | 25 +--- .../display/tegra/nvidia,tegra20-epp.yaml | 13 +++ .../display/tegra/nvidia,tegra20-gr2d.yaml | 13 +++ .../display/tegra/nvidia,tegra20-gr3d.yaml | 107 +++++++++++++++++- .../display/tegra/nvidia,tegra20-hdmi.yaml | 10 ++ .../display/tegra/nvidia,tegra20-host1x.yaml | 19 +++- .../display/tegra/nvidia,tegra20-isp.yaml | 12 ++ .../display/tegra/nvidia,tegra20-mpe.yaml | 15 +++ .../display/tegra/nvidia,tegra20-tvo.yaml | 7 ++ .../display/tegra/nvidia,tegra20-vi.yaml | 18 ++- 12 files changed, 215 insertions(+), 34 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml index afc283796653..0188baad0865 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml @@ -14,9 +14,6 @@ description: | The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP and DP outputs.
- See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information - regarding the DPAUX pad controller bindings. - properties: $nodename: pattern: "^sor@[0-9a-f]+$" diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml index eeffb8d7c597..ac346af663cd 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -59,6 +59,13 @@ properties: iommus: maxItems: 1
+ operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + nvidia,head: $ref: /schemas/types.yaml#/definitions/uint32 description: The number of the display controller head. This is used to setup the various diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml index abab8783db1b..75546f250ad7 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml @@ -11,9 +11,6 @@ maintainers: - Jon Hunter jonathanh@nvidia.com
properties: - $nodename: - pattern: "^dsi@[0-9a-f]+$" - compatible: oneOf: - enum: @@ -50,15 +47,12 @@ properties: items: - const: dsi
+ operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + power-domains: maxItems: 1
- '#address-cells': - const: 1 - - '#size-cells': - const: 0 - avdd-dsi-csi-supply: description: phandle of a supply that powers the DSI controller
@@ -90,17 +84,8 @@ properties: gang up with in order to support up to 8 data lanes $ref: "/schemas/types.yaml#/definitions/phandle"
-patternProperties: - "^panel@[0-9]+$": - type: object - properties: - reg: - maxItems: 1 - - required: - - reg - allOf: + - $ref: "../dsi-controller.yaml#" - if: properties: compatible: @@ -142,7 +127,7 @@ allOf: required: - interrupts
-additionalProperties: false +unevaluatedProperties: false
required: - compatible diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml index d6c45a385c89..0d55e6206b5e 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml @@ -40,6 +40,19 @@ properties: iommus: maxItems: 1
+ interconnects: + maxItems: 4 + + interconnect-names: + maxItems: 4 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + additionalProperties: false
examples: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml index f431a23a1373..984a0de9b8a8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml @@ -43,6 +43,19 @@ properties: iommus: maxItems: 1
+ interconnects: + maxItems: 4 + + interconnect-names: + maxItems: 4 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the HEG or core power domain + additionalProperties: false
examples: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml index 956d1f507208..4177d311899b 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml @@ -32,18 +32,77 @@ properties: maxItems: 2
resets: - minItems: 1 - maxItems: 2 + minItems: 2 + maxItems: 4
reset-names: + minItems: 2 + maxItems: 4 + + iommus: minItems: 1 maxItems: 2
- iommus: + interconnects: + minItems: 4 + maxItems: 10 + + interconnect-names: + minItems: 4 + maxItems: 10 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: minItems: 1 maxItems: 2
+ power-domain-names: + minItems: 2 + maxItems: 2 + allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra20-gr2d + then: + properties: + clocks: + items: + - description: module clock + + clock-names: + items: + - const: 3d + + resets: + items: + - description: module reset + - description: memory client hotflush reset + + reset-names: + items: + - const: 3d + - const: mc + + iommus: + maxItems: 1 + + interconnects: + minItems: 4 + maxItems: 4 + + interconnect-names: + minItems: 4 + maxItems: 4 + + power-domains: + items: + - description: phandle to the TD power domain + - if: properties: compatible: @@ -76,8 +135,36 @@ allOf: - const: mc2
iommus: + minItems: 2 maxItems: 2 - else: + + interconnects: + minItems: 8 + maxItems: 8 + + interconnect-names: + minItems: 8 + maxItems: 8 + + power-domains: + items: + - description: phandle to the TD power domain + - description: phandle to the TD2 power domain + + power-domain-names: + items: + - const: 3d0 + - const: 3d1 + + dependencies: + power-domains: [ power-domain-names ] + + - if: + properties: + compatible: + contains: + const: nvidia,tegra114-gr2d + then: properties: clocks: items: @@ -100,6 +187,18 @@ allOf: iommus: maxItems: 1
+ interconnects: + minItems: 10 + maxItems: 10 + + interconnect-names: + minItems: 10 + maxItems: 10 + + power-domains: + items: + - description: phandle to the TD power domain + additionalProperties: false
examples: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml index 4384803b9017..035b9f1f2eb5 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml @@ -50,6 +50,13 @@ properties: items: - const: hdmi
+ operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + hdmi-supply: description: supply for the +5V HDMI connector pin
@@ -76,6 +83,9 @@ properties: description: phandle of a display panel $ref: "/schemas/types.yaml#/definitions/phandle"
+ "#sound-dai-cells": + const: 0 + additionalProperties: false
required: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml index 4870d2130581..4fd513efb0f7 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -71,11 +71,13 @@ properties: - const: host1x
resets: + minItems: 1 # MC reset is optional on Tegra186 and later items: - description: module reset - description: memory client hotflush reset
reset-names: + minItems: 1 # MC reset is optional on Tegra186 and later items: - const: host1x - const: mc @@ -84,17 +86,20 @@ properties: maxItems: 1
interconnects: - description: Description of the interconnect paths for the host1x - controller; see ../interconnect/interconnect.txt for details. items: - description: memory read client for host1x
interconnect-names: - description: A list of names identifying each entry listed in the - "interconnects" property. items: - const: dma-mem # read
+ operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the HEG or core power domain + required: - compatible - interrupts @@ -133,6 +138,12 @@ allOf: - description: physical base address and length of the register region used by the hypervisor
+ resets: + maxItems: 1 + + reset-names: + maxItems: 1 + required: - reg-names
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml index f94f30830bbf..3bc3b22e98e1 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml @@ -38,6 +38,18 @@ properties: iommus: maxItems: 1
+ interconnects: + items: + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # write + + power-domains: + items: + - description: phandle to the VENC or core power domain + additionalProperties: false
examples: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml index 4dbbba3678ae..4154ae01ad13 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -41,6 +41,21 @@ properties: iommus: maxItems: 1
+ interconnects: + minItems: 6 + maxItems: 6 + + interconnect-names: + minItems: 6 + maxItems: 6 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the MPE power domain + additionalProperties: false
examples: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml index c1d4c6fe923f..467b015e5700 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml @@ -30,6 +30,13 @@ properties: items: - description: module clock
+ operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + additionalProperties: false
required: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 5cb2d9964c05..782a4b10150a 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -47,6 +47,21 @@ properties: iommus: maxItems: 1
+ interconnects: + minItems: 4 + maxItems: 5 + + interconnect-names: + minItems: 4 + maxItems: 5 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the VENC power domain + "#address-cells": const: 1
@@ -56,9 +71,6 @@ properties: ranges: maxItems: 1
- power-domains: - maxItems: 1 - avdd-dsi-csi-supply: description: DSI/CSI power supply. Must supply 1.2 V.