Enable Plane Degamma for ICL.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/intel_color.c | 86 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index afb1d00..504c046 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -615,6 +615,89 @@ static void broadwell_load_plane_luts(const struct drm_plane_state *state) INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); }
+static void icl_load_plane_degamma_lut(const struct drm_plane_state *state, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + if (icl_is_hdr_plane(dev_priv, plane)) { + lut_size = 128; + if (state->degamma_lut) { + struct drm_color_lut_ext *lut = + (struct drm_color_lut_ext *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(lut[i].red, + 24); + u32 lut_val = (word & 0x7ffffffff) >> 8; + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), + lut_val); + } + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + drm_color_lut_extract_ext(lut[i].red, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + drm_color_lut_extract_ext(lut[i].green, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + drm_color_lut_extract_ext(lut[i].blue, 24)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + (1 << 24) - 1); + } + } else { + lut_size = 32; + if (state->degamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), + lut[i].green); + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } + } +} + +/* Loads the palette/gamma unit for the CRTC on Gen11+. */ +static void icl_load_plane_luts(const struct drm_plane_state *state) +{ + icl_load_plane_degamma_lut(state, 0); +} + static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); @@ -978,6 +1061,9 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.color_commit = ilk_color_commit; }
+ if (INTEL_GEN(dev_priv) >= 11) + dev_priv->display.load_plane_luts = icl_load_plane_luts; + /* Enable color management support when we have degamma & gamma LUTs. */ if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)