On Tue, Jun 2, 2020 at 5:52 AM Maxime Ripard maxime@cerno.tech wrote:
Hi Eric,
On Wed, May 27, 2020 at 09:33:44AM -0700, Eric Anholt wrote:
On Wed, May 27, 2020 at 8:49 AM Maxime Ripard maxime@cerno.tech wrote:
In order to prevent timeouts and stalls in the pipeline, the core clock needs to be maxed at 500MHz during a modeset on the BCM2711.
Like, the whole system's core clock?
Yep, unfortunately...
How is it reasonable for some device driver to crank the system's core clock up and back down to some fixed-in-the-driver frequency? Sounds like you need some sort of opp thing here.
That frequency is the minimum rate of that clock. However, since other devices have similar requirements (unicam in particular) with different minimum requirements, we will switch to setting a minimum rate instead of enforcing a particular rate, so that patch would be essentially s/clk_set_rate/clk_set_min_rate/.
clk_set_min_rate makes a lot more sense to me. r-b with that obvious change. Thanks!