[PATCH v2 04/21] drm/dp: Track link capabilities alongside settings

2 Sep 2019

From: Thierry Reding treding@nvidia.com
Store capabilities in max_* fields and add separate fields for the
currently selected settings.
Cc: Rob Clark robdclark@gmail.com
Reviewed-by: Andrzej Hajda a.hajda@samsung.com
Signed-off-by: Thierry Reding treding@nvidia.com
---
 drivers/gpu/drm/bridge/tc358767.c      | 14 ++++++-------
 drivers/gpu/drm/drm_dp_helper.c        | 16 ++++++++++-----
 drivers/gpu/drm/msm/edp/edp_ctrl.c     |  8 ++++----
 drivers/gpu/drm/rockchip/cdn-dp-core.c |  8 ++++----
 drivers/gpu/drm/rockchip/cdn-dp-reg.c  | 13 ++++++------
 drivers/gpu/drm/tegra/dpaux.c          |  8 ++++----
 drivers/gpu/drm/tegra/sor.c            | 28 +++++++++++++-------------
 include/drm/drm_dp_helper.h            | 15 +++++++++-----
 8 files changed, 60 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index cebc8e620820..733fca7d3829 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -437,7 +437,7 @@ static u32 tc_srcctrl(struct tc_data *tc)
    	reg |= DP0_SRCCTRL_SCRMBLDIS;	/* Scrambler Disabled */
    if (tc->link.spread)
    	reg |= DP0_SRCCTRL_SSCG;	/* Spread Spectrum Enable */
-	if (tc->link.base.num_lanes == 2)
+	if (tc->link.base.lanes == 2)
    	reg |= DP0_SRCCTRL_LANES_2;	/* Two Main Channel Lanes */
    if (tc->link.base.rate != 162000)
    	reg |= DP0_SRCCTRL_BW27;	/* 2.7 Gbps link */
@@ -674,9 +674,9 @@ static int tc_get_display_props(struct tc_data *tc)
    	tc->link.base.rate = 270000;
    }
-	if (tc->link.base.num_lanes > 2) {
+	if (tc->link.base.lanes > 2) {
    	dev_dbg(tc->dev, "Falling to 2 lanes\n");
-		tc->link.base.num_lanes = 2;
+		tc->link.base.lanes = 2;
    }
ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
@@ -698,7 +698,7 @@ static int tc_get_display_props(struct tc_data *tc)
    dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
    	tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
    	(tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
-		tc->link.base.num_lanes,
+		tc->link.base.lanes,
    	(tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
    	"enhanced" : "non-enhanced");
    dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
@@ -906,7 +906,7 @@ static int tc_main_link_enable(struct tc_data *tc)
/* Setup Main Link */
    dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
-	if (tc->link.base.num_lanes == 2)
+	if (tc->link.base.lanes == 2)
    	dp_phy_ctrl |= PHY_2LANE;
ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
@@ -1094,7 +1094,7 @@ static int tc_main_link_enable(struct tc_data *tc)
    	ret = -ENODEV;
    }
-	if (tc->link.base.num_lanes == 2) {
+	if (tc->link.base.lanes == 2) {
    	value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
if (value != DP_CHANNEL_EQ_BITS) {
@@ -1291,7 +1291,7 @@ static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
    	return MODE_CLOCK_HIGH;
req = mode->clock * bits_per_pixel / 8;
-	avail = tc->link.base.num_lanes * tc->link.base.rate;
+	avail = tc->link.base.lanes * tc->link.base.rate;
if (req > avail)
    	return MODE_BAD;
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f5af71ec1b7d..365de63a02fb 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -342,9 +342,12 @@ static void drm_dp_link_reset(struct drm_dp_link *link)
    	return;
link->revision = 0;
-	link->rate = 0;
-	link->num_lanes = 0;
+	link->max_rate = 0;
+	link->max_lanes = 0;
    link->capabilities = 0;
+
+	link->rate = 0;
+	link->lanes = 0;
 }
/**
@@ -370,12 +373,15 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
    	return err;
link->revision = values[0];
-	link->rate = drm_dp_bw_code_to_link_rate(values[1]);
-	link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
+	link->max_rate = drm_dp_bw_code_to_link_rate(values[1]);
+	link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
if (values[2] & DP_ENHANCED_FRAME_CAP)
    	link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
+	link->rate = link->max_rate;
+	link->lanes = link->max_lanes;
+
    return 0;
 }
 EXPORT_SYMBOL(drm_dp_link_probe);
@@ -462,7 +468,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
    int err;
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
-	values[1] = link->num_lanes;
+	values[1] = link->lanes;
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
    	values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c
index 7f3dd3ffe2c9..4b31bc30be2c 100644
--- a/drivers/gpu/drm/msm/edp/edp_ctrl.c
+++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c
@@ -403,7 +403,7 @@ static void edp_fill_link_cfg(struct edp_ctrl *ctrl)
    u32 prate;
    u32 lrate;
    u32 bpp;
-	u8 max_lane = ctrl->dp_link.num_lanes;
+	u8 max_lane = ctrl->dp_link.max_lanes;
    u8 lane;
prate = ctrl->pixel_rate;
@@ -413,7 +413,7 @@ static void edp_fill_link_cfg(struct edp_ctrl *ctrl)
     * By default, use the maximum link rate and minimum lane count,
     * so that we can do rate down shift during link training.
     */
-	ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate);
+	ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.max_rate);
prate *= bpp;
    prate /= 8; /* in kByte */
@@ -701,7 +701,7 @@ static int edp_link_rate_down_shift(struct edp_ctrl *ctrl)
rate = ctrl->link_rate;
    lane = ctrl->lane_cnt;
-	max_lane = ctrl->dp_link.num_lanes;
+	max_lane = ctrl->dp_link.max_lanes;
bpp = ctrl->color_depth * 3;
    prate = ctrl->pixel_rate;
@@ -759,7 +759,7 @@ static int edp_do_link_train(struct edp_ctrl *ctrl)
     * Set the current link rate and lane cnt to panel. They may have been
     * adjusted and the values are different from them in DPCD CAP
     */
-	dp_link.num_lanes = ctrl->lane_cnt;
+	dp_link.lanes = ctrl->lane_cnt;
    dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate);
    dp_link.capabilities = ctrl->dp_link.capabilities;
    if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index d505ea7d5384..c500be895e64 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -478,7 +478,7 @@ static int cdn_dp_disable(struct cdn_dp_device *dp)
    cdn_dp_clk_disable(dp);
    dp->active = false;
    dp->link.rate = 0;
-	dp->link.num_lanes = 0;
+	dp->link.lanes = 0;
    if (!dp->connected) {
    	kfree(dp->edid);
    	dp->edid = NULL;
@@ -570,7 +570,7 @@ static bool cdn_dp_check_link_status(struct cdn_dp_device *dp)
    struct cdn_dp_port *port = cdn_dp_connected_port(dp);
    u8 sink_lanes = drm_dp_max_lane_count(dp->dpcd);
-	if (!port || !dp->link.rate || !dp->link.num_lanes)
+	if (!port || !dp->link.rate || !dp->link.lanes)
    	return false;
if (cdn_dp_dpcd_read(dp, DP_LANE0_1_STATUS, link_status,
@@ -953,7 +953,7 @@ static void cdn_dp_pd_event_work(struct work_struct *work)
    /* Enabled and connected with a sink, re-train if requested */
    } else if (!cdn_dp_check_link_status(dp)) {
    	unsigned int rate = dp->link.rate;
-		unsigned int lanes = dp->link.num_lanes;
+		unsigned int lanes = dp->link.lanes;
    	struct drm_display_mode *mode = &dp->mode;
DRM_DEV_INFO(dp->dev, "Connected with sink. Re-train link\n");
@@ -966,7 +966,7 @@ static void cdn_dp_pd_event_work(struct work_struct *work)
/* If training result is changed, update the video config */
    	if (mode->clock &&
-		    (rate != dp->link.rate || lanes != dp->link.num_lanes)) {
+		    (rate != dp->link.rate || lanes != dp->link.lanes)) {
    		ret = cdn_dp_config_video(dp);
    		if (ret) {
    			dp->connected = false;
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
index 077c87021908..7b254d0d0ba2 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
@@ -536,7 +536,7 @@ static int cdn_dp_get_training_status(struct cdn_dp_device *dp)
    	goto err_get_training_status;
dp->link.rate = drm_dp_bw_code_to_link_rate(status[0]);
-	dp->link.num_lanes = status[1];
+	dp->link.lanes = status[1];
err_get_training_status:
    if (ret)
@@ -561,7 +561,7 @@ int cdn_dp_train_link(struct cdn_dp_device *dp)
    }
DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->link.rate,
-			  dp->link.num_lanes);
+			  dp->link.lanes);
    return ret;
 }
@@ -659,14 +659,13 @@ int cdn_dp_config_video(struct cdn_dp_device *dp)
    do {
    	tu_size_reg += 2;
    	symbol = tu_size_reg * mode->clock * bit_per_pix;
-		do_div(symbol, dp->link.num_lanes * link_rate * 8);
+		do_div(symbol, dp->link.lanes * link_rate * 8);
    	rem = do_div(symbol, 1000);
    	if (tu_size_reg > 64) {
    		ret = -EINVAL;
    		DRM_DEV_ERROR(dp->dev,
    			      "tu error, clk:%d, lanes:%d, rate:%d\n",
-				      mode->clock, dp->link.num_lanes,
-				      link_rate);
+				      mode->clock, dp->link.lanes, link_rate);
    		goto err_config_video;
    	}
    } while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
@@ -680,7 +679,7 @@ int cdn_dp_config_video(struct cdn_dp_device *dp)
/* set the FIFO Buffer size */
    val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
-	val /= (dp->link.num_lanes * link_rate);
+	val /= (dp->link.lanes * link_rate);
    val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
    val += 2;
    ret = cdn_dp_reg_write(dp, DP_VC_TABLE(15), val);
@@ -833,7 +832,7 @@ static void cdn_dp_audio_config_i2s(struct cdn_dp_device *dp,
    u32 val;
if (audio->channels == 2) {
-		if (dp->link.num_lanes == 1)
+		if (dp->link.lanes == 1)
    		sub_pckt_num = 2;
    	else
    		sub_pckt_num = 4;
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index a0f6f9b0d258..ec1688bdff8d 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -792,14 +792,14 @@ int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
    if (tp == DP_TRAINING_PATTERN_DISABLE)
    	return 0;
-	for (i = 0; i < link->num_lanes; i++)
+	for (i = 0; i < link->lanes; i++)
    	values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
    		    DP_TRAIN_PRE_EMPH_LEVEL_0 |
    		    DP_TRAIN_MAX_SWING_REACHED |
    		    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
-				link->num_lanes);
+				link->lanes);
    if (err < 0)
    	return err;
@@ -811,13 +811,13 @@ int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
switch (tp) {
    case DP_TRAINING_PATTERN_1:
-		if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
+		if (!drm_dp_clock_recovery_ok(status, link->lanes))
    		return -EAGAIN;
break;
case DP_TRAINING_PATTERN_2:
-		if (!drm_dp_channel_eq_ok(status, link->num_lanes))
+		if (!drm_dp_channel_eq_ok(status, link->lanes))
    		return -EAGAIN;
break;
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index e1669ada0a40..cb94091d98a7 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -649,7 +649,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
    if (err < 0)
    	return err;
-	for (i = 0, value = 0; i < link->num_lanes; i++) {
+	for (i = 0, value = 0; i < link->lanes; i++) {
    	unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
    			     SOR_DP_TPG_SCRAMBLER_NONE |
    			     SOR_DP_TPG_PATTERN_TRAIN1;
@@ -670,7 +670,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
    value |= SOR_DP_SPARE_MACRO_SOR_CLK;
    tegra_sor_writel(sor, value, SOR_DP_SPARE0);
-	for (i = 0, value = 0; i < link->num_lanes; i++) {
+	for (i = 0, value = 0; i < link->lanes; i++) {
    	unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
    			     SOR_DP_TPG_SCRAMBLER_NONE |
    			     SOR_DP_TPG_PATTERN_TRAIN2;
@@ -685,7 +685,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
    if (err < 0)
    	return err;
-	for (i = 0, value = 0; i < link->num_lanes; i++) {
+	for (i = 0, value = 0; i < link->lanes; i++) {
    	unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
    			     SOR_DP_TPG_SCRAMBLER_GALIOS |
    			     SOR_DP_TPG_PATTERN_NONE;
@@ -912,11 +912,11 @@ static int tegra_sor_compute_config(struct tegra_sor *sor,
    u32 num_syms_per_line;
    unsigned int i;
-	if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
+	if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
    	return -EINVAL;
-	output = link_rate * 8 * link->num_lanes;
    input = pclk * config->bits_per_pixel;
+	output = link_rate * 8 * link->lanes;
if (input >= output)
    	return -ERANGE;
@@ -959,7 +959,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor,
    watermark = div_u64(watermark + params.error, f);
    config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
    num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
-			    (link->num_lanes * 8);
+			    (link->lanes * 8);
if (config->watermark > 30) {
    	config->watermark = 30;
@@ -979,12 +979,12 @@ static int tegra_sor_compute_config(struct tegra_sor *sor,
    if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
    	config->hblank_symbols -= 3;
-	config->hblank_symbols -= 12 / link->num_lanes;
+	config->hblank_symbols -= 12 / link->lanes;
/* compute the number of symbols per vertical blanking interval */
    num = (mode->hdisplay - 25) * link_rate;
    config->vblank_symbols = div_u64(num, pclk);
-	config->vblank_symbols -= 36 / link->num_lanes + 4;
+	config->vblank_symbols -= 36 / link->lanes + 4;
dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
    	config->vblank_symbols);
@@ -1830,17 +1830,17 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
    /* power DP lanes */
    value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
-	if (link.num_lanes <= 2)
+	if (link.lanes <= 2)
    	value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
    else
    	value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
-	if (link.num_lanes <= 1)
+	if (link.lanes <= 1)
    	value &= ~SOR_DP_PADCTL_PD_TXD_1;
    else
    	value |= SOR_DP_PADCTL_PD_TXD_1;
-	if (link.num_lanes == 0)
+	if (link.lanes == 0)
    	value &= ~SOR_DP_PADCTL_PD_TXD_0;
    else
    	value |= SOR_DP_PADCTL_PD_TXD_0;
@@ -1849,7 +1849,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
    value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
-	value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
+	value |= SOR_DP_LINKCTL_LANE_COUNT(link.lanes);
    tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
/* start lane sequencer */
@@ -1906,7 +1906,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
    	dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
rate = drm_dp_link_rate_to_bw_code(link.rate);
-	lanes = link.num_lanes;
+	lanes = link.lanes;
value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
    value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
@@ -1924,7 +1924,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
/* disable training pattern generator */
-	for (i = 0; i < link.num_lanes; i++) {
+	for (i = 0; i < link.lanes; i++) {
    	unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
    			     SOR_DP_TPG_SCRAMBLER_GALIOS |
    			     SOR_DP_TPG_PATTERN_NONE;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 935f331e6e72..9c675bde11e8 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1359,17 +1359,22 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
/**
- * struct drm_dp_link - DP link capabilities
+ * struct drm_dp_link - DP link capabilities and configuration
  * @revision: DP specification revision supported on the link
- * @rate: maximum clock rate supported on the link
- * @num_lanes: maximum number of lanes supported on the link
+ * @max_rate: maximum clock rate supported on the link
+ * @max_lanes: maximum number of lanes supported on the link
  * @capabilities: bitmask of capabilities supported on the link
+ * @rate: currently configured link rate
+ * @lanes: currently configured number of lanes
  */
 struct drm_dp_link {
    unsigned char revision;
-	unsigned int rate;
-	unsigned int num_lanes;
+	unsigned int max_rate;
+	unsigned int max_lanes;
    unsigned long capabilities;
+
+	unsigned int rate;
+	unsigned int lanes;
 };
int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
-- 
2.22.0


    

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[PATCH v2 04/21] drm/dp: Track link capabilities alongside settings