Hi Geert,
On Wed, Jun 23, 2021 at 03:09:06PM +0200, Geert Uytterhoeven wrote:
On Wed, Jun 23, 2021 at 2:58 PM Laurent Pinchart wrote:
On Wed, Jun 23, 2021 at 02:53:33PM +0200, Geert Uytterhoeven wrote:
On Wed, Jun 23, 2021 at 1:11 AM Kieran Bingham wrote:
From: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
Extend the Renesas DU display bindings to support the r8a779a0 V3U.
Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
Thanks for your patch!
--- a/Documentation/devicetree/bindings/display/renesas,du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -39,6 +39,7 @@ properties: - renesas,du-r8a77980 # for R-Car V3H compatible DU - renesas,du-r8a77990 # for R-Car E3 compatible DU - renesas,du-r8a77995 # for R-Car D3 compatible DU
- renesas,du-r8a779a0 # for R-Car V3U compatible DUreg: maxItems: 1
@@ -774,6 +775,57 @@ allOf: - reset-names - renesas,vsps
- if:
properties:compatible:contains:enum:- renesas,du-r8a779a0- then:
properties:clocks:items:- description: Functional clock for DU0- description: Functional clock for DU1clock-names:items:- const: du.0- const: du.1The hardware block has only a single function clock for both channels, like on R-Car H1.
And what about DU_DOTCLKIN?
As far as I can tell, there's no DU_DOTCLKIN in V3U.
See Table 6.13 of the Hardware User's Manual, pin IPC_CLKIN.
Maybe that's incorrect ? There's no mention of DU_DOTCLKIN anywhere else, and the DU bits that allow selection of the input clocks list the value documented for Gen3 SoCs as selected DU_DOTCLKIN as reserved.
Note that the register bits to configure it are present in drivers/pinctrl/renesas/pfc-r8a779a0.c, but the actual pin group is missing.