CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following: 1. Adds the core function to program CSC correction values for CHV/BSW platform 2. Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Signed-off-by: Kausal Malladi Kausal.Malladi@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 5 ++ drivers/gpu/drm/i915/intel_color_manager.c | 110 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 20 ++++++ 3 files changed, 135 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b95862e..9bf5720 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7916,11 +7916,16 @@ enum skl_disp_power_wells { #define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) #define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) #define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000) +#define PIPEA_CGM_CSC (VLV_DISPLAY_BASE + 0x67900) +#define PIPEB_CGM_CSC (VLV_DISPLAY_BASE + 0x69900) +#define PIPEC_CGM_CSC (VLV_DISPLAY_BASE + 0x6B900) #define _PIPE_CGM_CONTROL(pipe) \ (_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL)) #define _PIPE_GAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA)) #define _PIPE_DEGAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA)) +#define _PIPE_CSC_BASE(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC))
#endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index bd60fad..e855d5d 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,108 @@
#include "intel_color_manager.h"
+s16 get_csc_s3_12_format(s64 csc_value) +{ + s32 csc_int_value; + u32 csc_fract_value; + s16 csc_s3_12_format; + + if (csc_value >= 0) { + csc_value += CHV_CSC_FRACT_ROUNDOFF; + if (csc_value > CHV_CSC_COEFF_MAX) + csc_value = CHV_CSC_COEFF_MAX; + } else { + csc_value = -csc_value; + csc_value += CHV_CSC_FRACT_ROUNDOFF; + if (csc_value > CHV_CSC_COEFF_MAX + 1) + csc_value = CHV_CSC_COEFF_MAX + 1; + csc_value = -csc_value; + } + + csc_int_value = csc_value >> CHV_CSC_COEFF_SHIFT; + csc_int_value <<= CHV_CSC_COEFF_INT_SHIFT; + if (csc_value < 0) + csc_int_value |= CSC_COEFF_SIGN; + csc_fract_value = csc_value; + csc_fract_value >>= CHV_CSC_COEFF_FRACT_SHIFT; + csc_s3_12_format = csc_int_value | csc_fract_value; + + return csc_s3_12_format; +} + +int chv_set_csc(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + struct drm_ctm *csc_data; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_mode_config *config = &dev->mode_config; + u32 reg; + enum pipe pipe; + s32 word, temp; + int ret, count = 0; + + if (!blob) { + DRM_ERROR("NULL Blob\n"); + return -EINVAL; + } + + if (blob->length != sizeof(struct drm_ctm)) { + DRM_ERROR("Invalid length of data received\n"); + return -EINVAL; + } + + csc_data = (struct drm_ctm *)blob->data; + if (csc_data->version != CHV_CSC_DATA_STRUCT_VERSION) { + DRM_ERROR("Invalid CSC Data struct version\n"); + return -EINVAL; + } + + pipe = to_intel_crtc(crtc)->pipe; + + /* Disable CSC functionality */ + reg = _PIPE_CGM_CONTROL(pipe); + I915_WRITE(reg, I915_READ(reg) & (~CGM_CSC_EN)); + + DRM_DEBUG_DRIVER("Disabled CSC Functionality on Pipe %c\n", + pipe_name(pipe)); + + reg = _PIPE_CSC_BASE(pipe); + while (count < CSC_MAX_VALS) { + word = get_csc_s3_12_format(csc_data->ctm_coeff[count]); + + /* + * Last value to be written in 1 register. + * Otherwise, each pair of CSC values go + * into 1 register + */ + if (count != (CSC_MAX_VALS - 1)) { + count++; + temp = get_csc_s3_12_format(csc_data->ctm_coeff[count]); + word |= temp; + } + I915_WRITE(reg, word); + reg += 4; + count++; + } + + DRM_DEBUG_DRIVER("All CSC values written to registers\n"); + + /* Enable CSC functionality */ + reg = _PIPE_CGM_CONTROL(pipe); + I915_WRITE(reg, I915_READ(reg) | CGM_CSC_EN); + DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe)); + + ret = drm_property_replace_global_blob(dev, &blob, + sizeof(struct drm_ctm), (void *) csc_data, + &crtc->base, config->prop_ctm); + if (ret) { + DRM_ERROR("Error updating CSC blob\n"); + return -EFAULT; + } + + return ret; +} + int chv_set_degamma(struct drm_device *dev, struct drm_property_blob *blob, struct drm_crtc *crtc) { @@ -295,6 +397,14 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, DRM_DEBUG_DRIVER( "DeGamma registers Commit success!\n"); } + + blob = crtc_state->ctm_blob; + if (blob) { + ret = chv_set_csc(dev, blob, crtc); + if (!ret) + DRM_DEBUG_DRIVER( + "CSC registers Commit success!\n"); + } } }
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 6a4fff2..b2ee847 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -54,6 +54,26 @@ #define CHV_DEGAMMA_MSB_SHIFT 2 #define CHV_DEGAMMA_GREEN_SHIFT 16
+/* CSC correction */ +#define CHV_CSC_DATA_STRUCT_VERSION 1 +/* + * Fractional part is 32 bit, and we need only 12 MSBs for programming + * into registers. ROUNDOFF is required to minimize loss of precision. + */ +#define CHV_CSC_FRACT_ROUNDOFF (1 << 19) +/* + * CSC values are 64-bit values. For CHV, the maximum CSC value that + * user can program is 7.99999..., which can be represented in fixed point + * S31.32 format like this, with all fractional bits as 1 + */ +#define CHV_CSC_COEFF_MAX 0x00000007FFFFFFFF +#define CHV_CSC_COEFF_SHIFT 32 +#define CHV_CSC_COEFF_INT_SHIFT 28 +#define CSC_COEFF_SIGN (1 << 31) +#define CHV_CSC_COEFF_FRACT_SHIFT 20 +#define CSC_MAX_VALS 9 + /* CHV CGM Block */ #define CGM_GAMMA_EN (1 << 2) +#define CGM_CSC_EN (1 << 1) #define CGM_DEGAMMA_EN (1 << 0)