27 Aug
2015
27 Aug
'15
5:08 p.m.
Tobias Jakobi wrote:
Next I looked into Jerome's question about whethere the G2D is cache coherent with the CPU. I looked into old Android code and found FIMG2D_AXI_MODE_REG, a register that currently isn't touched in the DRM code. It seems to manipulate signals to the AXI Master interface.
The register looks like this: [0:3] ARCACHE [4:7] AWCACHE [8:15] ARUSERS [16:23] AWUSERS [24:25] MaxBurstLength
Correction, it looks like this: [0:3] ARCACHE [4:7] AWCACHE [8:12] ARUSERS [16:20] AWUSERS [24:25] MaxBurstLength (the rest of the bits are reserved)
With best wishes, Tobias