On 04/04/18 12:51, Laurent Pinchart wrote:
Hi Tomi,
On Wednesday, 4 April 2018 10:37:05 EEST Tomi Valkeinen wrote:
On 04/04/18 00:11, Laurent Pinchart wrote:
I assume access to DMM-mapped buffers to be way more frequent than access to the DMM registers. If that's the case, this partial workaround should only slightly lower the probability of system lock-up. Do you have plans to implement a workaround that will fix the problem completely ?
CPU only accesses memory via DMM when using TILER 2D buffers, which are not officially supported. For non-2D, the pages are mapped directly to the CPU without DMM in between.
What is the DMM used for with non-2D then ? Does it need to be setup at all ?
It creates a contiguous view of memory for IPs without IOMMUs, like DSS.
Tomi