On Mon, Feb 28, 2022 at 09:29:52PM -0800, Matt Roper wrote:
Platforms with FlatCCS do not use auxiliary planes for compression control data and thus do not need traditional aux table invalidation (and the registers no longer even exist).
Original-author: CQ Tang Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 28 ++++++++++++++++-------- 1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 1f8cf4f790b2..13bbbf5d9737 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -231,7 +231,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) { u32 flags = 0;
u32 *cs;
u32 *cs, count;flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -246,7 +246,12 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
cs = intel_ring_begin(rq, 8 + 4);
if (!HAS_FLAT_CCS(rq->engine->i915))count = 8 + 4;elsecount = 8;
u32 count = 8;
...
if (!HAS_FLAT_CCS(rq->engine->i915)) count += 4;
would probably be shorter, or even
cs = intel_ring_begin(rq, HAS_FLAT_CCS(...) ? 12 : 8)
but doesn't really matter
Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com
Lucas De Marchi